• Title/Summary/Keyword: 가상 프로토타이핑

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Design and Implementation for Integrated Development Environment Interface Based on RAPID (RAPID 기반의 통합개발환경 인터페이스 설계 및 구현)

  • Lee, Jeong-Bae;Seo, Il-Soo
    • Convergence Security Journal
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    • v.9 no.2
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    • pp.59-69
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    • 2009
  • In this paper, Integrated development environments interface was designed and implemented for the integrated development environments. By using connection interface, Integration between physical prototyping and virtual prototyping which has different characteristics each other could be possible. Specially, good performance of the connection interface was showed by testing result of operation implemented.

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Virtual Prototyping of Progrmmable Logic Controller based Real-time Systems (PLC를 적용한 실시간 시스템의 가상 프로토타이핑)

  • 천성욱;강순주서대화
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.735-738
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    • 1998
  • To develop an effective virtual prototyping methodology for the PLC(Programmable Logic Controller) based real-time systems, a conversion algorithm from RLL(Relay Ladder Logic) to statechart is presented in this paper. The RLL is the main programming language to represent the operation of the PLC, and the statechart is the most widely used tool in the field of virtual prototyping in order to represent the behaviour of real-time systems. A virtual prototyping for an example case is implemened to evaluate the benefit of the proposed algorithm.

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컴포넌트기반 분산형 가상대학 구축 사례

  • 임승린
    • KSCI Review
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    • v.9 no.1
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    • pp.9-15
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    • 2002
  • 본 대학에서는 2001 재정지원사업 중 특성화 프로그램으로 "수원.화성지역 정보화 지원을 위한 원격교육센터 구축" 사업을 추진하고 있다. 총 4단계로 계획된 본 계획의 제1단계로 구축할 시스템의 프로토타이핑을 수행하는 것을 2001년도 사업 목표로 정하고 추진하였다. 본 사업은 인터넷정보과에서 추진하고 있으며 학과가 처한 여러 가지 상황에 대처하기 위한 일종의 생존 전략중 하나이다. 구상하고 있는 시스템은 완전 분산형을 추구하고 있으며 향후 확장성이나 시스템 구축의 효율을 고려하여 분석 및 설계단계에서는 UML을 기반으로하는 RUP방법을 채택하고 있으며 구현부분에서는 시스템 구성 요소를 분해하여 컴포넌트화 하고 있다. 또한 모든 문서화는 ETRI에서 제공하고 있는 방법론인 마르미 III를 채택하고 있다. 본 논문에서는 현재 구축중인 시스템에 대한 배경에서 향후 계획까지 포괄적으로 소개하여 향후 유사한 프로젝트를 구상하고 있는 조직이나 개인에게 도움을 주고자한다.도움을 주고자한다.

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Application of practical education program of sensor instrumentation engineering using NI-ELVIS (NI-ELVIS를 활용한 센서계측공학의 실습교육 사례)

  • Lee, Byeung-Leul;Lee, Yong-Hee
    • The Journal of Korean Institute for Practical Engineering Education
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    • v.3 no.1
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    • pp.76-83
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    • 2011
  • In this paper we suggest an effective teaching plan for measurement engineering by utilizing the NI-ELVIS(National Instrument Educational Laboratory Virtual Instrumentation Suite). ELVIS is a development platform for LabVIEW-based design and prototyping environment. It consists of LabVIEW-based virtual instruments, a multifunctional data acquisition device, and a custom-designed benchtop workstation and prototyping board. Therefore it can replace the expensive instruments for the effective education in the area of electrical engineering. This platform can be applicable for the sensor instrumentation engineering study, though it is a multidisciplinary learning including electrical engineering, sensor technology, signal processing and data analysis. We hope this approach can be used for the other educational area related the electrical experimental education.

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Improvement of Product Development Process Based on Integrated CAE Application : Case Study on Washing Machine Development (통합적 CAE 적용을 통한 제품 설계 프로세스 개선 : 세탁기 개발 사례 중심)

  • 김석관;김태영;조용석;임원길;장성기
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1996.11a
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    • pp.846-850
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    • 1996
  • Today's product development requires simultaneous satisfaction of low cost, high quality and fast time to market. It is, however, difficult for product designers and engineers to achieve this goal due to too many requirements. This study shows integrated Computer Aided Engineering (CAE) approach can help to achieve such goal. CAE can not only support designers when decision needs to be made during concept design period but also provide evaluation of the designed parts and guidance to the best design of products during detail design period. Furthermore, integration with virtual prototyping concept can reduce number of actual prototyping and consequently reduce product development cost and time considerably. In order to demonstrate its possibility, example of washing machine development using CAE and its results are presented in this study.

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Automatic Block-Type Assembly Structure Construction and Editing System (블록형 구조물 자동 생성 및 구축 시스템 개발)

  • Kim, Jae Woo;Kang, Kyung-Kyu;Lee, Man Hee;Lee, Jongwook;Lee, JiHyung
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2016.01a
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    • pp.219-222
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    • 2016
  • 블록형 구조물의 구축은 완구의 목적으로 널리 사용되고 있으며 이외에도 제품 디자인을 위한 래피드 프로토타이핑 및 창의학습을 위한 도구로도 활용되고 있다. 본 논문은 블록형 구조물을 적은 비용으로 손쉽게 설계하고 구축하기 위하여 블록형 구조물 자동 생성 기능 및 편집 기능을 제공하는 소프트웨어 시스템을 개발하였다. 본 시스템을 이용하여 가상공간에서 자유롭게 블록형 구조물을 생성 및 편집할 수 있고, 실제 구조물의 조립을 위한 매뉴얼로 활용할 수 있다.

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VIP/Sim : Design and Implementation of Virtual Prototyping Simulator based on Statecharts (VIP/Sim : Statecharts에 기반을 둔 가상 프로토타이핑 시뮬레이터 설계 및 구현)

  • Kim, Cheol-Ung;Han, Sang-Yong;Choe, Jin-Yeong;Lee, Jeong-A
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.3
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    • pp.891-900
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    • 2000
  • A Visual development framework for embedded system is presented based on virtual prototyping. Embedded systems often are used in life critical situation, where reliability is very important. Time_to_market, correctness, user_friendly_design are another features required for embedded system design. However, embedded systems are today designed with an ad hoc approach that is heavily based on earlier experience with similar products. We believe that new design paradigm is needed and it should be based on the use of formal model and visual system to describe the behavior of the system at a high level abstraction. Virtual prototyping has all the required features. It has the following advantages; correct design, clear interface definition, idea experimentation, increased communication. In this paper, we describe the design and implementation of VIP/Sim(Virtual Prototyping Simulator), a visionary development framework for embedded system design. New feature such as state polymorphism is augmented to the de_facto standard formal language, statechart, for enhanced dynamic modeling. Actual design experience with VIP/Sim is also discussed.

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LAPG-2: A Cost-Efficient Design Verification Platform with Virtual Logic Analyzer and Pattern Generator (LAPG-2: 가상 논리 분석기 및 패턴 생성기를 갖는 저비용 설계 검증 플랫폼)

  • Hwang, Soo-Yun;Kang, Dong-Soo;Jhang, Kyoung-Son;Yi, Kang
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.5
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    • pp.231-236
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    • 2008
  • This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves $55%{\sim}99%$ of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.

Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems (모바일 내장형 시스템을 위한 듀얼-포트SDRAM의 성능 평가 및 최적화)

  • Yang, Hoe-Seok;Kim, Sung-Chan;Park, Hae-Woo;Kim, Jin-Woo;Ha, Soon-Hoi
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.5
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    • pp.542-546
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    • 2008
  • Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.