• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.156-163
• /
• 2012

Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.201-208
• /
• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.96-106
• /
• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.12
• /
• pp.161-168
• /
• 2016

Thanks to mass production and provision of smartphones and the HMD (head mounted display), VR (virtual reality) is now being applied to various areas. The VR HMD is the interface equipment which allows users to have realistic experiences through human sensory organs such as vision and auditory sense. Since the majority of VR equipment is operated by the display for both eyes, 360-degree video content and the depth information, the VR mechanism is closely related to human senses, especially vision. Previous studies have focused on how to minimize negative impact such as motion sickness or visual fatigue. Little attention has been paid on research about the visual treatment. Therefore, the focus of this study is to develop technical elements for utilization of vision therapy with the VR HMD and explore possible areas to apply it. To this end, we analyzed the past case studies and technical elements to identify 16 areas for vision therapy. We also developed the optical parameters for utilization of the VR HMD visual targets. The result of this study is expected to be utilized for development of visual targets for vision therapy based on the VR HMD.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.18 no.6
• /
• pp.642-653
• /
• 2008

This study deals with modeling of head-related transfer functions(HRTFs) using principal components analysis(PCA) in the time and frequency domains. Four PCA models based on head-related impulse responses(HRIRs), complex-valued HRTFs, augmented HRTFs, and log-magnitudes of HRTFs are investigated. The objective of this study is to compare modeling performances of the PCA models in the least-squares sense and to show the theoretical relationship between the PCA models. In terms of the number of principal components needed for modeling, the PCA model based on HRIR or augmented HRTFs showed more efficient modeling performance than the PCA model based on complex-valued HRTFs. The PCA model based on HRIRs in the time domain and that based on augmented HRTFs in the frequency domain are shown to be theoretically equivalent. Modeling performance of the PCA model based on log-magnitudes of HRTFs cannot be compared with that of other PCA models because the PCA model deals with log-scaled magnitude components only, whereas the other PCA models consider both magnitude and phase components in linear scale.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.25 no.5
• /
• pp.321-328
• /
• 2015

In recent years, there has been an increasing demand to apply the new IACS(International Association of Classification Societies) standards for ice and polar-classed ships. For ice-class vessel propulsion system, the ice impact torque design criterion is defined as a periodic harmonic function in relation to the number of the propeller blades. However, irregular or transient ice impact torque is assumed to occur likely in actual circumstances rather than these periodic loadings. In this paper, the reliability and torsional vibration characteristics of a comparatively large six-cylinder marine diesel engine for propulsion shafting system was examined and reviewed in accordance with current regulations. In this particular, the transient ice impact torque and excessive vibratory torque originating from diesel engine were interpreted and the resonant points identified through theoretical analysis. Several floating ice impacts were carried out to evaluate torque responses using the calculation method of classification rule requirement. The Newmark method was used for the transient response analysis of the whole system.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.5
• /
• pp.48-61
• /
• 2017

An IaaS service of a cloud computing environment makes itself attractive for running large scale parallel application thanks to its innate characteristics that a user can utilize a desired number of high performance virtual machines without maintenance cost. The total execution time of a parallel application on a high performance computing environment depends on a task scheduling algorithm. Most studies on task scheduling algorithms on cloud computing environment try to reduce a user cost, and studies on task scheduling algorithms that try to reduce total execution time are rarely carried out. In this paper, we propose a task scheduling algorithm called an HAGD and a performance enhancement method called a group task duplication method of which the HAGD utilizes. The group task duplication method simplifies previous task duplication method, and the HAGD uses the group task duplication method or a task insertion method according to the characteristics of a computing environment and an application. We found that the proposed algorithm provides superior performance regardless of the characteristics in terms of normalized total execution time through performance evaluations.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.9
• /
• pp.12-20
• /
• 2001

The ATM-PON has an important meaning at next generation access network because the equipment transmits various types of user traffic with a single platform through the passive optical splitter. Ranging is a technology to place all ONUs at the same virtual distance in order to provide the synchronization for the upstream signal in the ATM-PON based on the Time Division Multiplexing (TDM). In this paper, we review the merits of ATM PON and related protocol for the PON operation. We summarize and analyze the steps about the ranging protocol based on ITU-T G.983.1 and implement a simulator that can simulate the ranging procedure based on our modeling. In this paper, we can investigate time requirements of G.983.1 by using the simulator and find out the wasted rate of the bandwidth during the ranging procedure in order to know the influence for ONUs while ATM-PON is in-service. Also, we show that a new ranging scheme reducing window size can avoid the degradation of quality of service of ONUs in service with simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.26-31
• /
• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.4
• /
• pp.49-58
• /
• 2011

Typically, vision-based AR systems operate on the basis of prior knowledge of the environment such as a square marker. The traditional marker-based AR system has a limitation that the marker has to be located in the sensing range. Therefore, there have been considerable research efforts for the techniques known as real-time camera tracking, in which the system attempts to add unknown 3D features to its feature map, and these then provide registration even when the reference map is out of the sensing range. In this paper, we describe a real-time camera tracking framework specifically designed to track a monocular camera in a desktop workspace. Basic idea of the proposed scheme is that a real-time camera tracking is achieved on the basis of a plane tracking algorithm. Also we suggest a method for re-detecting features to maintain registration of virtual objects. The proposed method can cope with the problem that the features cannot be tracked, when they go out of the sensing range. The main advantage of the proposed system are not only low computational cost but also convenient. It can be applicable to an augmented reality system for mobile computing environment.