• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.719-721
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• 2012

본 시험은 군전자장비의 전원제어부품으로 사용되는 TPS54315소자에 대하여 과도방사선에 따른 과도응답특성인 Upset/Latch-up특성을 평가하기 시험으로 포항가속기 연구소내의 Test LINAC 조사시설을 이용하여 $1.43{\times}10^7$rad(si)/sec~$1.25{\times}10^8$rad(si)/sec 선량률 조건에서의 실측시험을 수행하였다. 시험결과 $1.0{\times}10^8$rad(si)/sec 이후 Latch-up 현상이 확인되었으며 연속펄스 인가 시 Latch-up상태에서 정상상태로 복귀하는 결과를 확인하였다. 또한 이러한 현상은 과도방사선에 의한 광전류가 내부전원 Reset로직을 트리거 시킴으로써 Latch-up상태에서의 전원바이어스를 일시적으로 차단함에 따라 발생된 것으로 본 실험을 통하여 Reset회로가 내장된 소자의 경우 일부 Latch-up현상과 동시에 Reset회로가 트리거 되는 경우 Latch-up상태에서 정상상태로 복귀되는 결과를 확인하였다.

• Journal of Mechanical Science and Technology
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• 제20권12호
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• pp.2025-2033
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• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.283-285
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• 2001

In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.164-167
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• 1994

In this Study, we design the process of 0.1$\mu\textrm{m}$ gate length CMOS that is immunized against Latch-up, and investigate the characteristic of Latch-up of this device by the design rule of layout. Using TSUPREM4 and MEDICI, we design the device and simulate the variable characteristics of it we could understand that the characteristic of Latch-up is changed for the better by varying the critical factor of it. We also investigate the structure of CMOS that can be immunized against Latch-up.

• 대한전자공학회논문지
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• 제22권5호
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• pp.50-56
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• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

• 대한전기학회논문지
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• 제44권2호
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• pp.222-227
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• 1995

A new IGBT structure, which may suppress latch-up phenomena considerably, is proposed and verified by MEDICI simulation. The proposed structure employing the segmented $n^{+}$ buffer layer increases latch-up current capability due to suppression of the current flowing through the resistance of $p^{-}$ well, $R_{p}$, which is the main cause of latch-up phenomena without degradation of forward characteristics. The length of the $n^{+}$ buffer layer is investigated by considering the trade-off between the latch-up current capability and the forward voltage drop. The segmented $N^{+}$ buffer layer results in better latch-up immunity in comparison with the uniform buffer layer.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• 전기학회논문지
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• 제59권11호
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• pp.2089-2092
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• 2010

There are many cases that interrupt the production process because of malfunctions caused by electronic circuit boards which control equipment, but it is difficult to distinctly identify the causes in many cases. Especially, CMOS devices with the control logic circuit return automatically to normal state after their own faults. Therefore it is not easy to analyze the problems with electronic circuit boards. Recently, nuclear power plant experienced a failure due to the malfunction of electronic circuit boards and it was identified that the reason of the malfunction was because of latch-up phenomenon caused by external surge in electronic devices. This paper presents the causes and the phenomenon of latch-up by experiment and also a way using counter EMF diodes, noise filters and surge protective devices to prevent latch-up phenomenon from electronic circuit boards, finally confirms the effectiveness of the result by experiment.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2013년도 추계학술대회 논문집
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• pp.519-524
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• 2013

The purpose of this study is that developing the index which evaluate sound quality of door latch and improving its sound quality through that results. For that, various operating sound of door latch was used for jury test. Loudness and sharpness related metrics are dominant in sound quality index we developed. This research investigate the main transfer path of its operating sound through sound field visualization and get conclusion that could reduce the impact sound of door latch. Therefore, we could verify sound quality improvement of modified product by using sound quality index.