• 제목/요약/키워드: , multiplexer

검색결과 292건 처리시간 0.022초

서로 다른 임계압력을 가지는 디지털 밸브가 설치된 제어라인을 이용한 3 진 유체분배기 (A Ternary Microfluidic Multiplexer using Control Lines with Digital Valves of Different Threshold Pressures)

  • 이동우;조영호
    • 대한기계학회논문집A
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    • 제33권6호
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    • pp.568-572
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    • 2009
  • We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

PERFORMANCE ANALYSIS OF AAL MULTIPLEXER WITH CBR TRAFFIC AND BURSTY TRAFFIC

  • Park, Chul-Geun;Han, Dong-Hwan
    • Journal of applied mathematics & informatics
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    • 제8권1호
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    • pp.81-95
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    • 2001
  • This paper models and evaluates the AAL multiplexer to analyze AAL protocol in ATM networks. We consider an AAL multiplexer in which a single periodically determinsitic CBR traffic stream and several variable size bursty background traffic streams are multiplexed and one ATM cell stream goes out. We model the AAL multiplexer as a B/sup X/ + D/D/1/K queue and analyze this queueing system. We represent various performance measures such as loss probability and waiting time in the basis of cell and packet.

Ku-대역 위성중계기용 도파관 Manifold 멀티플렉서 설계 (Implementation of Waveguide Manifold Multiplexer for Ku-band Satellite Transponder)

  • 정근욱;이재현
    • 전자공학회논문지A
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    • 제32A권6호
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    • pp.787-798
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    • 1995
  • We implement the E-plane T-juncition manifold mutiplexer having low insertion loss for output multiplexer of Ku-band satellite transponder. Manifold multiplexer implemented here is composed of 2 channel filters, T-junctions, half-wave waveguide connecting channel filters and manifold, and manifold itself.[1-4] Considering the mass and volume of the satellite transponder, the channel filters are designed to dual-mode.[5-13] And Elliptic filter function is used, which has good characteristics of suppressing the interference between 2 channels. Since the performance of manifold multiplexer depends on the manifold waveguide transmission line length, it's necessary proper analysis. In this paper, we do optimization process of T-junction and other elements by using CAD and implement the manifold multiplexer. An experiment shows that characteristic response of multiplexer matches wel its modeling result.

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기가주파수대 멀티플렉서 설계에 관한 연구 (Study of the Multigigabit Multiplexer Design)

  • 김학선;최병하;이형재
    • 한국통신학회논문지
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    • 제15권2호
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    • pp.147-154
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    • 1990
  • 갈륨비소를 사용한 SCFL을 채택하여 4:1 시분할 멀티플랙서를 설계하였다. 설계된 멀티플렉서는 2:1 시분할 주파수 분할기를 사용하여 2:1 멀티플렉서 2단을 사용하였다. 시뮬레이션 결과, 최고 동작 주파수는 6.25GHz이었고 전력소모는 192mW이었다. 따라서 최대 출력 bit율은 12.5Gbit/sec를 얻었다. 이 결과 기존의 멀티플렉서에 비해 속도 및 전력소모 면에서 상당히 개선된 것이다.

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임베디드 플렛폼 기반 미국향 모바일방송 다중화기 설계 및 구현 (Implementation of An Embedded Platform-Based ATSC Mobile Broadcasting Multiplexer)

  • 권기원;박경원;김현식;이연성
    • 대한임베디드공학회논문지
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    • 제6권2호
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    • pp.93-99
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    • 2011
  • In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

The Design of a Multiplexer for Multiview Image Processing

  • Kim, Do-Kyun;Lee, Yong-Joo;Koo, Gun-Seo;Lee, Yong-Surk
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -1
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    • pp.682-685
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    • 2002
  • In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

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다중화기 기반 논리 설계를 위한 무정의 조건의 고찰 (아두이노 설계 교육에의 활용을 위한) (Consideration of Don't-care Condition for Multiplexer-based Logic Design (For Application to Arduino-based Design Education))

  • 이재민
    • 디지털콘텐츠학회 논문지
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    • 제18권5호
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    • pp.881-888
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    • 2017
  • 다중화기를 이용한 논리설계는 구조적 디지털 시스템 설계에서 설계의 편리성과 유연성을 위한 유용한 방법으로 사용되어왔다. 본 논문에서는 다중화기(multiplexer : MUX) 기반 논리설계에서 종래의 연구들에서 세밀히 다루지 않았던 무정의 조건(don't care condition)이 논리최적화에 미치는 영향을 분석해보고 단일 다중화기 기반의 설계와 복수 다중화기 기반의 설계를 위한 무정의 조건의 활용방법을 제시한다. 특히 데이터 입력의 개수가 $2^m$개보다 적은 경우(선택선의 개수는 m개일 때)의 설계방법을 고찰한다. 제시하는 기법을 디지털논리설계 교육과 관련하여 최근 창의적 공학교육에서 크게 활용되고 있는 아두이노(Arduino)를 이용한 마이크로프로세서 설계와 연계하여 활용하는 방법에 대해서도 기술한다.

Design of LTPS TFT Current Mode Multiplexer and MUX-based Logic Gates

  • Jeong, Ju-Young;Hong, Moon-Pyo
    • Journal of Information Display
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    • 제9권3호
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    • pp.1-7
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    • 2008
  • With the aim of creating a high-quality display system with value-added functions, we designed a current mode multiplexer for LTPS TFT devices. The multiplexers had less than 1 volt logic swing, and speed improvement was evident compared with that of conventional CMOS architecture. We refined the multiplexer to achieve a more stable current steering operation. By using the versatility of the multiplexer, a new NAND/AND and NOR/OR logic gates were designed through the simple modification of signal connections. Two micron LTPS TFT parameters were used during the HSPICE simulation of the circuits.

쉐이퍼를 사용한 비디오 트래픽원의 다중화기 성능 분석 (Performance Analysis of the Multiplexer for Shaped Video Traffic Sources)

  • 이상천;홍정완;김제승
    • 산업공학
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    • 제18권4호
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    • pp.494-503
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    • 2005
  • This paper considers the problem of performance analysis for the multiplexer, when homogeneous periodic on-off sources are statistically multiplexed. Periodic on-off source model is defined that on-period and off-period are repeated by once in a deterministic periodic time and in on-period, cell arrives with deterministic time interval. In order to reflect periodicity of source model, we consider two multiplexing situation, such as random multiplexing and synchronized multiplexing. In both case, we obtain the overload-period distribution in the multiplexer, and an approximate method using the overload period distribution is suggested for obtaining the CLP(Cell Loss Probability) in the buffer of the multiplexer. A numerical example using MPEG-I real traffic samples and the results are also presented.

Multiplexer as selector to select different speed (Normal speed, High speed and Super high speed) to display CAR at different speed to color TV system

  • Adhikari, Ganesh
    • International Journal of Advanced Culture Technology
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    • 제10권3호
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    • pp.332-338
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    • 2022
  • The article presents a concept of designing a Multiplexer circuit which acts as a "Selector" and that becomes capable to select different speed created at different TTL Gate configurations; Standard TTL(Normal Speed), High Speed TTL(High Speed), Schottky TTL(Super High Speed) and further connect the selected Gate speed to the CAR shape created using C-Programming at Computer Graphics and finally CAR shape display at different speed to the color TV. The Multiplexer supporting efficient and more reliable selection criteria using "Logical based selection criteria" and further the output from multiplexer is provided to CAR shape created using c-programming and finally CAR shape is display to color TV system. Basic purposes and assumptions regarding the design and development of this system as well as a description of its operation have been presented.