• 충청수학회지
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• 제25권3호
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• pp.445-453
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• 2012

In this paper, we introduce the concept of multiplier in a Hilbert algebra and obtained some properties of multipliers. Also, we introduce the simple multiplier and characterized the kernel of multipliers in Hilbert algebras.

• 충청수학회지
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• 제30권4호
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• pp.357-367
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• 2017

In this paper, we introduce the notion of multiplier of AC-algebra and consider the properties of multipliers in AC-algebras. Also, we characterized the fixed set $Fix_d(X)$ by multipliers. Moreover, we prove that M(X), the collection of all multipliers of AC-algebras, form a semigroup under certain binary operation.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제6권2호
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• pp.75-84
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• 2002

Using good properties of an optimal normal basis of type I in a finite field ${\mathbb{F}}_{2^m}$, we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing $xy^2$. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware architecture for a bit serial multiplication of two elements in ${\mathbb{F}}_{2^m}$.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2000년도 가을 학술발표회 논문집
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• pp.253-260
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• 2000

Pile foundations have been widely used in civil engineering construction for many years. Structures subjected to large lateral loads usually have pile foundations as shallow foundations cannot sometimes support the moments on these structure. The purpose of this paper is to propose the p - multiplier factor (P$\sub$M/) based on the characteristics of behavior of laterally loaded group pile in homogeneous sand. For this, a series of model tests are performed and the composite analytical method proposed by author is used to the propose P$\sub$M/. Based on the model test results of the large number of laterally loaded group piles, p - multiplier factors for homogeneous sand are proposed by back analysis under various condition of soil density, spacing-to-diameter ratio of pile, number of pile, and spacing-to-diameter of pile. P - multiplier approach provides a simple but sufficient tool for characterizing the shadowing group effects of laterally loaded group pile.

• 충청수학회지
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• 제29권4호
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• pp.613-629
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• 2016

In this paper, we introduced the notion of multiplier of Boolean algebras and discuss related properties between multipliers and special mappings, like dual closures, homomorphisms on B. We introduce the notions of xed set $Fix_f(X)$ and normal ideal and obtain interconnection between multipliers and $Fix_f(B)$. Also, we introduce the special multiplier ${\alpha}_p$a nd study some properties. Finally, we show that if B is a Boolean algebra, then the set of all multipliers of B is also a Boolean algebra.

• 대한수학회논문집
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• 제18권1호
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• pp.59-63
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• 2003

Let A be a $C^*$-algebra and $K_{A}$ its Pedersen's ideal. A is called a PCS-algebra if the multiplier $\Gamma(K_{A})\;of\;K_{A}$ is the multiplier M(A) of A. J. Mack [5]characterized PCS-algebras by weak compactness on the spectrum of A. We give a new simple proof of this Mack's result using the concept of semicontinuity and N. C. Phillips' description of $\Gamma(K_{A})$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.658-661
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• 2002

An analog multiplier-divider circuit that realized through the use of OTAs, which does not require external passive circuit elements and temperature compensated, is proposed in this paper. Since the scheme is realized in such a way that employs only OTA as a standard cell, the circuit is simple and can be easily constructed from commercially available IC. The circuit bandwidth is wide and close to the transistor f$\sub$T/. Simulation results that demonstrate the performances of the multiplier-divider circuit are included.

• 전자공학회논문지B
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• 제31B권3호
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• pp.60-68
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• 1994

In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.79-82
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials in existence coefficients over finite field GF(3$^{m}$ ). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of (m+1)$^2$identical cells, each cell consists of single mod(3) additional gate and single mod(3) multiplicative gate. Proposed multiplier need single mod(3) multiplicative gate delay time and m mod(3) additional gate delay time not clock. Also, the proposed architecture is simple, regular and has the property of modularity, therefore well-suited for VLSI implementation.