• 제목/요약/키워드: $SiO_2/Si$ interface

검색결과 593건 처리시간 0.03초

$N_2$O 분위기에서 RTP로 제조한 실리콘 산화막의 산화 반응 (Oxidation Reaction of silicon Oxids fabricated by Rapid Thermal Process in $N_2$O ambient)

  • 박진성;이우성;심태언
    • 한국재료학회지
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    • 제3권1호
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    • pp.7-11
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    • 1993
  • 실리콘 산화막을 $N_2$O 분위기에서 RTP로 제조하여 그 성장 기구를 고찰 했다. 산화막과 기판 실리콘 계면 사이에 질소성분이 포함된 oxynitride층이 존재한다. $N_2$O 기체를 이용한 산화막 성장은 삼화제 확산에 의해 성장이 지배되는 포물선 성장론을 따르고 산화제 확산 억제작용은 실리콘 산화막과 실리콘 기판사이에 존재하는 oxynitride막에서 일어난다. 확산이 산화막 성장을 결정하는 구간에서 포물선 성장율 상수 B의 활성화 에너지는 약 1.5 eV이고 산화막 두께 증가에 따라 증가한다.

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다결정 실리콘 TFT에 대한 수소처리 영향 (Hydroquenation Effects on the Poly-Si TFT)

  • 하형찬;이상규;고철기
    • 전자공학회논문지A
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    • 제30A권1호
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    • pp.23-30
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    • 1993
  • Hydrogenation on the top gate and bottom gate Poly-Si TET's was performed by using Nh$_{3}$ plasma and annealing SiN film deposited by PECVD and then the electric characteristics on Poly-Si TET were investigated. As the time of NA$_{3}$ plasma treatment increaes, on/off current ratio gradually increases and the swing value decreases. The trap densities of graim boundaries in Poly-Si decrease very much during the inital 20min of hydrogenation time, and the decreasing scale becomes smaller after 20 min. The electric characteristics of the top gate TFT are better than those of the bottom gate TFT, it is considered due to the defects at the interface between the Poly-Si and the underlayer, SiO$_{2}$. After NH$_{3}$ plasma was treated for 2 hours for the top gate TFT, as the aging time atroon temperature increases on current was not scacely changed and off current decreases more than 1 order. Gate current density recovers to original value after the aging treatment for 8 days and then the electric characteristics are finally improved. It is suggested that the degraded characteristics of gate oxide are improved, from the variations of C-V characteristics with aging time. For the hydrogenation of isothermal and isochronal annealing SiN film deposited by PECVD, the characteristics of Poly-Si TFT are improved with increasing annealing temperature and are not largely changed with increasing annealing time. This results is good in agreement with the hydrogen reduction in Sin film as variations of annealing temperature and time.

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A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

  • Lyu, Jong-Son
    • ETRI Journal
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    • 제15권2호
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    • pp.11-25
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    • 1993
  • Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

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Nitoxide막에 의한 표면 불활성화에 관한 연구 (A Study on the passivation of Si by Thermal Ammonia Nitroxide)

  • 성영권;최종일;오재하
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1988년도 춘계학술대회 논문집
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    • pp.78-81
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    • 1988
  • Nitroxide films were made from the $NH_3$ gas nitridation of as-grown $SiO_2$. The electrical characterization results including C-V characteristics and BT stress generally indicate that the high field stress instability and insulator-substrate interfacial characteristics are improved by nitridation of $SiO_2$. A C-V technique was used to determine the surface state density $N_{55}$ and then $N_{55}$ in the nitroxide-substrate interface was $8{\times}10(/eVcm^2$). This $N_{55}$ is related with 1/f noise was revealed experimentally and relationship was plotted and 1/f noise characteristics were also improved by nitridation of of $SiO_2$By the results of measurements on these films show that very thin thermal silicon nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI device.

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고분자 기판위에 유기 용매를 사용하지 않은 다층 박막 Encapsulation 기술 개발 (Improvement of Permeation of Solvent-free Multi-Layer Encapsulation of thin films on Ethylene Terephthalate(PET))

  • 강희진;한진우;김종연;문현찬;최성호;박광범;김태하;김휘운;서대식
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 학술대회 및 기술세미나 논문집 디스플레이 광소자
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    • pp.56-57
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    • 2006
  • In this paper, the inorganic multi-layer thin film encapsulation was newly adopted to protect the organic layer from moisture and oxygen. Using the electron beam, Sputter, inorganic multi-layer thin-film encapsulation was deposited onto the Ethylene Terephthalate(PET) and their interface properties between inorganic and organic layer were investigated. In this investigation, the SiON SiO2 and parylene layer showed the most suitable properties. Under these conditions, the WVTR for PET can be reduced from a level of $0.57\;g/m^2/day$ (bare subtrate) to 1*10-5 g/$m^2$/day after application of a SiON and SiO2 layer. These results indicates that the PET/SiO2/SiON/Parylene barrier coatings have high potential for flexible organic light-emitting diode(OLED) applications.

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Pt/BLT/$CeO_2$/Si 구조를 이용한 MFIS의 특성 (Characteristics of MFIS using Pt/BLT/$CeO_2$/Si structures)

  • 이정미;김창일;김경태;김동표;황진호;이철인
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.186-189
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    • 2002
  • The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

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Metal/$Al_2O_3-SiO_2$ System Interface Investigations

  • Korobova, N.;Soh, Deawha
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2004년도 SMICS 2004 International Symposium on Maritime and Communication Sciences
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    • pp.70-73
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    • 2004
  • The packaging of the integrated circuits requires knowledge of ceramics and metals to accommodate the fabrication of modules that are used to construct subsystems and entire systems from extremely small components. Composite ceramics (Al$_2$O$_3$-SiO$_2$) were tested for substrates. A stress analysis was conducted for a linear work-hardening metal cylinder embedded in an infinite ceramic matrix. The bond between the metal and ceramic was established at high temperature and stresses developed during cooling to room temperature. The calculations showed that the stresses depend on the mismatch in thermal expansion, the elastic properties, and the yield strength and work hardening rate of the metal. Experimental measurements of the surface stresses have also been made on a Cu/Al$_2$O$_3$-SiO$_2$ceramic system, using an indentation technique. A comparison revealed that the calculated stresses were appreciably larger than the measured surface stresses, indicating an important difference between the bulk and surface residual stresses. However, it was also shown that porosity in the metal could plastically expand and permit substantial dilatational relaxation of the residual stresses. Conversely it was noted that pore clusters were capable of initiating ductile rupture, by means of a plastic instability, in the presence of appreciable tri-axiality. The role of ceramics for packaging of microelectronics will continue to be extremely challenging.

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용융상태에서의 silicon과 carbon의 반응에 관한 연구 (A study on th reaction between silicon in melt and carbon)

  • M.J. Lee;B.J. Kim;S.M. Kang;J.K. Choi;B.S. Jeon;Keun Ho Orr
    • 한국결정성장학회지
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    • 제4권4호
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    • pp.336-346
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    • 1994
  • 용융 silicon과 carbon 입자가 어떠한 반응관계를 나타내는가를 알아보기 위하여 sili-con만으로 된 powder와 silicon에 carbon을 0.2wt%의 비율로 혼합한 powder와 silicon에 carbon을 0.2wt%의 비율로 혼합한 powder를 silicon의 용융점 이사의 고온인 $1450^{\circ}C, 1550^{\circ}C, 1650^{\circ}C, 1700^{\circ}C$에서 각각 1시간, 4시간을 유지시킨 다음 quenching시켜 각각의 조건에 따른 반응의 정도 및 상의 분포와 morphology의 분석을 통해 melt sili-con의 morphology 변화,carbon이 함유된 silicon의 조건에 따른 물성변화 및 SiC의 형성여부를 조사하기 위하여 광학현미경과 SEM, XRD등을 이용하여 시편의 미세구조 및 결정화 양상을 관찰하였다. 용융점 이상의 온도에서 quartz는 연화하여 분해반응을 일으켜 산소를 내놓고 이것이 silicon과 결합하여 SiO로써 기체상태로 휘발하게 되어 silicon melt에 산소침투로 인항 표면결함을 형성하며, liquid silicon속에 용융되어 있던 carbonrhk 불순물로써 grain boundary를 따라 존재 하고 있는 미반응의 carbon이 용융상태 silicon과 반응하여 SiC를 형성한다. SiC 결정은 고화계 면에서 발생하게 되며 생성되는 결정은 ${\alpha}-SiC$이었다.

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RTA 후속 열처리에 의한 $Ta_{2}O_{5}-Si$ 계면 반응과 전기적 특성 변화 (Variations in electrical properties and interface reactions of $Ta_{2}O_{5}-Si$ by RTA post annealing)

  • 전석룡;이정엽;한성욱;박종완
    • 한국재료학회지
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    • 제5권3호
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    • pp.357-363
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    • 1995
  • PECVD(Plasma-enhanced Chemical Vapor Deposition)법을 이용하여 증착한 $Ta_{2}$O_{5}$ 박막의 전기적 특성과 미세구조에 미치는 RTA(Rapid Thermal annealing) 후속 고온 열처리의 영향을 조사하였다. $Ta_{2}$O_{5}$ 박막의 미세구조와 interface 거동을 관찰하기 위하여XRD(X-ray Diffractometer), TEM(Transmission Electron Microscope), AES(Auger Electron Spectroscope) 분석을 실시하였으며, 전기적 특성을 관찰하기 위하여 I-V, C-V 측정을 하였다. $600^{\circ}C$에서 60초간 열처리를 실시하였을 경우 가장 우수한 유전 특성 및 누설 전류 특성을 보였으며, 유전 상수는 26이었고 누설 전류는 5 $\times$ $10^{-11}$A/$cm^{2}$이었다. $600^{\circ}C$ 이상의 온도에서 행한 열처리에 의하여 박막의 누설 전류와 유전 특성은 복합적으로 영향을 받았음을 알 수 있었다. 이는 $600^{\circ}C$의 열처리에서 이루어지고있는 박막의 결함감소와 고밀화 현상과 함께 80$0^{\circ}C$ 이상의 열처리에서 발생하는 조밀육방정 결정 구조를 가지는 $\delta$-$Ta_{2}$O_{5}$의 결정화에 기인함을 알 수 있었다. 또한 TEM과 AES분석 결과로부터 이들 박막의 누설 전류와 유전상수의 변화는 열처리에 의하여 일어나는 Ta-O-Si transition층의 생성과 성장에 기인함을 알 수 있었다. 따라서 $Ta_{2}$O_{5}$ 박막의 전기적 특성의 변화는 RTA 후속 열처리에 따른 계면 반응과 결정화 그리고 박막의 조밀화에 그 영향이 있음을 알 수 있었다.

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Synthesis and Photocatalytic Properties of Thermally Stable Metal-Oxide Hybrid Nanocatalyst with Ultrathin Oxide Encapsulation

  • Naik, Brundabana;Moon, Song Yi;Kim, Sun Mi;Jung, Chan Ho;Park, Jeong Young
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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    • pp.317.2-317.2
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    • 2013
  • Ultrathin oxide encapsulated metal-oxide hybrid nanocatalysts have been fabricated by a soft chemical and facile route. First, SiO2 nanoparticles of 25~30 nm size have been synthesized by modified Stobber's method followed by amine functionalization. Metal nanoparticles (Ru, Rh, Pt) capped with polymer/citrate have been deposited on functionalized SiO2 and finally an ultrathin layer of TiO2 coated on surface which prevents sintering and provides high thermal stability while maximizing the metal-oxide interface for higher catalytic activity. TEM studies confirmed that 2.5 nm sized metal nanoparticles are well dispersed and distributed throughout the surface of 25 nm SiO2 nanoparticles with a 3-4 nm TiO2 ultrathin layer. The metal nanoparticles are still well exposed to outer surface, being enabled for surface characterization and catalytic activity. Even after calcination at $600^{\circ}C$, the structure and morphology of hybrid nanocatalysts remain intact confirm the high thermal stability. XPS spectra of hybrid nanocatalyst suggest the metallic states as well as their corresponding oxide states. The catalytic activity has been evaluated for high temperature CO oxidation reaction as well as photocatalytic H2 generation under solar simulation. The design of hybrid structure, high thermal stability, and better exposure of metal active sites are the key parameters for the high catalytic activity. The maximization of metal-TiO2 interface interaction has the great role in photocatalytic H2 production.

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