• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.198-198
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• 2013

Metal-Oxide-Semiconductor (MOS)에서 사용되는 다양한 channel materials로 high electron mobility을 가지는 III-V compound semiconductor가 대두되고 있다 [1,2]. 하지만 이러한 III-V compound semiconductor는 Si에 비해 안정적인 native oxide가 부족하기 때문에 Si, Ge, Al2O3과 BeO 등과 같은 다양한 물질들의 interface passivation layers (IPLs)에 대한 연구가 많이 되고 있다. 이러한 IPLs 물질은 0.5~1.0 nm의 매우 얇은 physical thickness를 가지고 있고 또한 chemical inert하기 때문에 플라즈마 식각에 대한 연구가 되고 있지만 IPLs 식각 후 기판인 III-V compound semiconductor에 physical damage과 substrate recess를 줄이기 위해서 높은 선택비가 필요하다. 이러한 식각의 대안으로 원자층 식각이 연구되고 있으며 이러한 원자층 식각은 반응성 있는 BCl3의 adsorption과 low energy의 Ar bombardment로 desorption으로 self-limited한 one monolayer 식각을 가능하게 한다. 그러므로 본 연구에서는, III-V compound semiconductor 위에 IPLs의 adsorption과 desorption의 cyclic process를 이용한 원자층식각으로 다양한 물질인 SiO2, Al2O3 (self-limited one monolayer etch rate=about 1 ${\AA}$/cycle), BeO (self-limited one monolayer etch rate=about 0.75 ${\AA}$/cycle)를 얻었으며 그 결과 precise한 etch depth control로 minimal substrate recess 식각을 할 수 있었다.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.973-976
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• 2006

In this paper, the inorganic multi-layer encapsulation of thin film was newly adopted to protect the organic layer from moisture and oxygen. Using the electron beam, Sputter, inorganic multi-layer thin-film encapsulation was deposited onto the Ethylene Terephthalate(PET) and their interface properties between inorganic and organic layer were investigated. In this investigation, the SiON $SiO_2$ and parylene layer showed the most suitable properties. Under these conditions, the water vapor transmission rate (WVTR) for PET can be reduced from level of $0.57g/m^2/day$ (bare substrate) to $1^{\ast}10^{-5}g/m^2/day$ after application of a SiON and $SiO_2$ layer. These results indicate that the $PET/SiO_2/SiON/Parylene$ barrier coatings have high potential for flexible organic light-emitting diode(OLED) applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• New & Renewable Energy
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• v.3 no.4
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• pp.63-68
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• 2007

유리를 기판으로 하는 superstrate pin 비정질 실리콘 태양전진에서 전면 투명전도막(TCO)과 p-층의 계면은 태양전지 변환효율에 큰 영향을 미친다. 면투명전도막(TCO)으로 현재 일반적으로 사용되는 ZnO:Al는 $SnO_2:F$보다 전기, 광학적으로 우수하고, 안개율 (Haze)높으며, 수소 플라즈마에서 안정성이 높은 특징을 갖고 있다. 그래서 박막 태양전지의 특성향상에 매우 유리하나, 태양전지로 제조했을 때, $SnO_2$보다 충진율(Fill Factor:F.F)과 $V_{oc}$가 감소한다는 단점을 가지고 있다. 본 실험실에서는 $SnO_2:F$dml F.F.가 72%이 나온 반면 ZnO:Al의 F.F은 68%에 그쳤다. 이들 원인을 분석하기 위해 TCO/p-layer의 전기적 특성을 알아 본 결과, $SnO_2:F$보다 ZnO:Al의 직렬저항이 높게 측정되었다. 이러한 결과를 바탕으로 p-layer에 $R=(H_2/SiH_4)=25$로 변화, p ${\mu}c$-Si:H/p a-SiC:H로 p-layer 이중 증착, p-layer의 boron doping 농도를 증가시키는 실험을 하였다. 직렬저항이 가장 낮았던 p ${\mu}c$-Si:H/p a-SiC:H 인 p-layer 이중 증착에서 $V_{oc}$는 0.95V F.F는 70%이상이 나왔다. 이들 각 p층의 $E_a$(Activiation Energy)를 구해본 결과, ${\mu}c$-Si:H의 Ea 가 가장 낮은 것을 관찰 할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.227-233
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• 2015

To reduce the cost of solar electricity, the crystalline-silicon (c-Si) photovoltaic industry is moving toward the use of thinner wafers (100 μm to 200 μm) to achieve a high efficiency. In this field, it is imperative to achieve an effective passivation method to reduce the electronic losses at the c-Si interface. In this article, we review the most promising surface passivation schemes that are available for high-efficiency solar cells.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1042-1048
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• 1990

The approximations of charge relationships at normally doped semiconductor interfaces were qualitatively derived basis on electrical neutrality conditions. Effects of ion adsorptions, activation processes, interfacial structures, rectifying phenomena, and effects of surface potential barriers at the p- and n-Si/CsNO3 aqueous electrolytes, and the p-Si/(1HF:3HNO3:6H2O) electrolyte solutions were investigated using a cyclic voltammetric method. The space charge acts the most important role for the pn junction structures, the rectifying phenomena, and the activation processes. The Current-Voltage (I-V) characteristics curves significantly depend on developing of the Helmholtz double layers and charging of the show surface states during the activation processes. A linear Current-Voltage characteristics region was observed at the p-Si/(1HF:3HNO3: 6H2O) electrolyte solution interface.

• Korean Journal of Optics and Photonics
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• v.3 no.4
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• pp.258-265
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• 1992

A low loss optical waveguide of $P_{2}O_{5}-SiO_{2}$on Si substrate is produced by using the chemical vapour deposition method of $SiO_2$ thin films used in Si technology. Propagation loss of the waveguide layer was 1.65 dB/cm as produced and reduced down to 0.1 dB/cm after heat treatment at $1100^{\circ}C$. By using laser lithography and reactive ion etching method $P_{2}O_{5}-SiO_{2}$ waveguide was produced and subsequently annealed at $1100^{\circ}C$.As a result of this annealing the shape of the waveguide core was changed from rectangular to semi-circular form, and the propagation loss was reduced as down to 0.03 dB/cm at 0.6328$\mu$m and 0.04dB/cm at 1.53$\mu$m. We think that the mechanism of the reduction in propagation loss during the heat treatment is the following: 1) The hydrogen bonding in waveguide layer, which causes absorption loss, is dissociated and diffused out. 2) The roughness of the interface and the micro-structure of the waveguide layer is removed. 3) The irregularities in the cross-sectional shape of the waveguide which was induced during the lithographic process were disappeared by flowing of the waveguide core.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.491-495
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• 1999

In this study, we focus on Ca contaminant which affects on the roughness Si substrate after thermal process. The initial Si substrates were contaminated intentionally by using a standard Ca solution. The contamination levels of Ca impurity were measured by TXRF and the chemical composition of that was analyzed by AES. Then we gre the thermal oxide to investigate the effect of Ca contaminants. The microroughness of the Si surface, the thermal oxide surface, and the surface after removing the thermal oxide were measured to examine the electrical characteristics. The initial substrates that were contaminated with the standard solution of Ca exhibited the contamination levels of 10\ulcorner~10\ulcorneratoms/$\textrm{cm}^2$ which was measured by TXRF. The Ca contaminants were detected by AES and exhibited the peaks of Ca, SI, C and O.After intentional contamination, the surface microroughness of this initial substrate was increased from $1.5\AA$ to 4$\AA$ as contamination levels became higher. The microroughness of the thermal oxide surfaces of both contaminated and bare Si substrates exhibits similar values. But the microroughness of the contaminated$ Si/SiO_2$ interface was increased as contamination increased. The thermal oxide of contaminated substrate exhibited the small minority carrier diffusion length, low breakdown voltage, and slightly high leakage current.