• Title/Summary/Keyword: $SiO_2$ layer

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일라이트의 비등방적 압축특성 연구 (A Study on Anisotropic Compression Behavior of Illite)

  • 윤서희;이용재
    • 광물과 암석
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    • 제33권1호
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    • pp.11-18
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    • 2020
  • 천연산 일라이트(K0.65Al2(Al0.65Si3.35)O10(OH)2) 분말 시료에 대해 물과 알코올(메탄올:에탄올 = 4:1 체적비, ME41)의 두 가지 압력매개체를 이용한 다이아몬드앤빌셀 고압 회절실험을 진행하였다. 물을 이용한 실험에서는 층간 유입을 유도하기 위해 약 250℃까지 열을 가하는 과정을 거치며 최대 약 2.7 GPa까지 압력을 가하였고, 알코올을 이용한 실험에서는 상온에서 최대 약 6.9 GPa까지 가압하면서 방사광 분말 회절법을 통해 시료의 압축특성을 관찰하였다. 위와 같은 조건에서는 층간의 확장이나 상전이는 관찰되지 않았다. 물과 알코올의 서로 다른 압력매개체 하에서 압축된 일라이트의 체적탄성률(K0)은 각각 45(3) GPa와 51(3) GPa로 도출되어 오차범위 내에서 크게 다르지 않음을 확인하였다. 또한 회절자료 분석결과 격자상수에 따른 선형압축률은 알코올 압력매개체일 때 βa, βb, βc의 값이 각각 0.0025 GPa-1, 0.0029 GPa-1, 0.0144 GPa-1로 도출되어 c-축의 압축률이 약 6배 큰 것으로 확인되었다. 본 연구에서 확인된 일라이트의 체적탄성률 및 선형압축률을 일라이트와 구조적으로 유사한 백운모와 비교하였다.

열 화학 기상 증착법을 이용한 삼극관 구조의 탄소 나노 튜브 전계 방출 소자의 제조 (Fabrication of Triode Type Field Emission Device Using Carbon Nanotubes Synthesized by Thermal Chemical Vapor Deposition)

  • 유완준;조유석;최규석;김도진
    • 한국재료학회지
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    • 제14권8호
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    • pp.542-546
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    • 2004
  • We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

Single layer antireflection coating on PET substrates for display applications

  • Gowtham, M.;Mangalaraj, D.;Seo, Chang-Ki;Shim, Myung-Suk;Hwang, Sun-Woo;Yi, Jun-Sin
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.988-991
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    • 2004
  • In the present investigation, we tried AR coating simulation by using the "Essential Macleod optical coating design and analysis" program. After various run of the program we selected appropriate materials which have specific refractive indices and for that thickness was optimized to get the low reflectance. By comparing the simulated results for the different materials,we found that $SiO_2$ and TiN are the appropriate materials for this Flat panel device (FPD) application. Thin films of these materials were deposited using RF magnetron sputtering and Inductively Coupled Plasma Chemical Vapour Deposition (ICPCVD) methods on Polyethyleneterephthalate (PET) substrates. Spectroscopic ellipsometer (SE MF-1000) and UV-Vis spectrophotometer (SCINCO) were used for the optical characterization. The obtained experimental results are in good agreement with the simulation results.

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플라즈마 전해산화 공정에 있어서 전해액 내 실리콘 이온이 표면특성에 미치는 영향

  • 김성철;윤상희;성기훈;강두홍;민관식;차덕준;김진태;윤주영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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    • pp.290-290
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    • 2013
  • 플라즈마 전해산화(Plasma Electrolytic Oxidation)란 저 농도의 알칼리 전해액을 매개로, 고전압을 가해 미세 플라즈마 방전을 유도하여 Al, Mg, Ti 등의 금속표면을 산화시켜 고내식성, 초경합금 수준의 내마모성, 탁월한 절연성과 고경도성을 가지는 산화막을 형성시키는 기술로 전자, 자동차, 의료, 섬유, 해양, 석유화학 산업에 이르기까지 광범위한 분야에 적용되어 우수한 물성을 확보할 수 있는 차세대의 표면처리 기술이다. 본 연구에서는 6061 알루미늄 합금을 이용하여 다양한 전해액 조건에서 플라즈마 전해산화 공정으로 Al2O3 산화막을 형성시켰다. 산화막의 조성 및 미세구조는 XRD와 FE-SEM, EDS를 이용하여 분석하였다. 형성된 산화막은 회색에서 밝은 회색으로 시편 전면에 고르게 나타났다. 전해액 조성을 바꾸어줌에 따라 각기 다른 표면 특성을 가지는 산화막을 얻을 수 있었고, 그에 따른 물성 변화를 분석하였다. 특히 Si 이온 농도를 조절함으로써 피막 성장인자와 표면 미세구조를 제어할 수 있었다.

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강진과 부안 청자 도편의 비교연구 (Comparative Study of Celadon Shards from Gangjin and Buan Kiln Sites)

  • 노형구;김수민;김응수;조우석;한정화
    • 한국세라믹학회지
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    • 제52권1호
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    • pp.41-47
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    • 2015
  • Celadon shards from Gangjin and Buan were analyzed for their color, chemistry and microstructures. They exhibited similar chromatic characteristics in a $CIEL^*a^*b^*$ analysis. All of the glazes assessed showed comparable compositional areas, while the bodies from Gangjin shards had higher $RO_2$ concentrations. A high degree of similarity was also noted in the microstructures of the glaze and bodies from both regions. Anorthite crystals appeared in the glaze layer, and phase separation behavior developed around these crystals. This may have been caused by the glaze chemistry and the sintering process given the lengthy heating and cooling time. A Raman analysis indicated higher isolated $SiO_4$ unit ($Q_0$) values for the Buan samples. This can stem from the higher firing temperature or the longer sintering process.

Device and Circuit Performance Issues with Deeply Scaled High-K MOS Transistors

  • Rao, V. Ramgopal;Mohapatra, Nihar R.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권1호
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    • pp.52-62
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    • 2004
  • In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

Organic Thin-Film Transistors Fabricated on Flexible Substrate by Using Nanotransfer Molding

  • Hwang, Jae-Kwon;Dang, Jeong-Mi;Sung, Myung-Mo
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2010년도 제39회 하계학술대회 초록집
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    • pp.287-287
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    • 2010
  • We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

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반도체소자의 Via hole 결함 측정을 위한 전자컬럼 제어기술 개발 (Development of microcolumn control unit to detect of via-hole defects on wafer)

  • 노영섭;김흥태;김호섭;김대욱;안승준;김영철;진상원;황남우
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.528-529
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    • 2008
  • A new concept based on sample current measurements for detecting of via-hole defects on wafer has been performed by low energy electron beam microcolumn. The microcolumn has been operated at a low voltage of 290 eV with total emission current of 400 nA, and a sample current of 6 nA. The test sample was fabricated with SiO2 layer of 300 nm thickness on a piece of a silicon substrate. Preliminary results of both sample current method and secondary electron method show microcolumn and its control can be useful technology for detecting of via-hole defects on wafer.

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지오폴리머 시멘트를 이용한 콘크리트 표면의 패각 분말 코팅 (Shell Powder Coating on the Surface of Concrete by Geopolymer Cement)

  • 김갑중;한현근;서동석;이종국
    • 한국재료학회지
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    • 제20권1호
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    • pp.1-6
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    • 2010
  • Geopolymer materials are attractive as inorganic binders due to their superior mechanical and eco-friendly properties. In the current study, geopolymer-based cement was prepared using aluminosilicate minerals from fly-ash with KOH as an alkaline-activator and $Na_2SiO_3$ as liquid glass. Then, calcium carbonate powder from a clam shell was mixed with the geopolymer and the mixture was coated on a concrete surface to provide points of attachment for environmental organisms to grow on the geopolymers. We investigated the effect of the shell powder grain size on the microstructure and bonding property of the geopolymers. A homogeneous geopolymer layer coated well on the concrete surface via aluminosilicate bonding, but the adhesiveness of the shell powder on the geopolymer cement was dependent on the grain size of the shell powder. Superior adhesive characteristics were shown in the shell powder of large grain size due to the deep penetration into the geopolymer by their large weight. This kind of coating can be applied to the adhesiveness of eco-materials on the surface of seaside or riverside blocks.

고 전력 DMOSFET 응용을 위한 트렌치 게이트 형성에 관한 연구 (A Study on the Formation of Trench Gate for High Power DMOSFET Applications)

  • 박훈수;구진근;이영기
    • 한국전기전자재료학회논문지
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    • 제17권7호
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    • pp.713-717
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    • 2004
  • In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.