• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.115-120
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• 2007

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) might be fabricated on the mica substrate and transferred to a flexible plastic substrate because mica can be easily cleaved into a thin layer. To overcome the adhesion and stress problem between poly-Si film and mica substrate, a buffer layer consisting of $SiO_x/Ta/Ti$ three layers has been developed. The $SiO_x$ layer is for electrical isolation, the Ti layer is for adhesion of $SiO_{x}$ and mica. and Ta is for stress relief between $SiO_x$ and Ti. A TFT was fabricated on the mica substrate by a conventional Si process and was successfully transferred to a plastic substrate.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2002.05a
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• pp.29-34
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• 2002

[ $Nb/MoSi_2-ZrO_2$ ] laminate composites have been successfully fabricated by alternately stacking $MoSi_2-ZrO_2$ powder layer and Nb sheet, followed by hot pressing in a graphite mould. The fabricating parameters were selected as hot press temperatures. The instrumented Charpy impact test was carried out at the room temperature in order to investigate the relationship between impact properties and fabricating temperatures. The interfacial shear strength between $MoSi_2-ZrO_2$ and Nb, which is associated with the fabricating temperature and the growth of interfacial reaction layer, is also discussed. The plastic deformation of Nb sheet and the interfacial delamination were macroscopically observed. The $Nb/MoSi_2-ZrO_2$ laminate composites had the maximum impact value when fabricated at 1623K, accompanying the increase of fracture displacement and crack propagation energy. The interfacial shear strength of $Nb/MoSi_2-ZrO_2$ laminate composites increased with the growth of interfacial reaction layer, which resulted from the increase of fabricating temperature. there is an appropriate interfacial shear strength for the enhancement of impact value of $Nb/MoSi_2-ZrO_2$ laminate composites. A large increase of interfacial shear strength restrains the plastic deformation of Nb sheet.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.

• Journal of the Korean Chemical Society
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• v.56 no.4
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• pp.478-483
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• 2012

We successfully synthesized $Fe_3O_4/SiO_2$ nanoparticles with ultrathin silica layer of $1.0{\pm}0.5$ nm that was fine controlled by changing concentration of $Fe_3O_4$. Among various reaction conditions for silica coating, increasing concentration of $Fe_3O_4$ was more effective approach to decrease silica thickness compared to water-to-surfactant ratio control. Moreover, we found that concentration of the 1-octanol is also important factor to produce the homogeneous $Fe_3O_4/SiO_2$ nanoparticles. The present approach could be available to apply on preparation of other core/shell nanoparticles with ultrathin silica layer.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.81-87
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• 2010

In this paper, we have fabricated $SiO_2$ oxidation thin films by HDP-CVD(high density plasma-chemical vapor deposition) method for passivation layer or barrier layer of OLED(organic light emitting diode). We have control and estimate the deposition rate and relative index characteristics with process parameters and get optimized conditions. They are gas flow rate($SiH_4:O_2$=30:60[sccm]), 70 [mm] distance from source to substrate and no-bias. The WVTR(water vapor transmission rate) is 2.2 [$g/m^2$_day]. Therefore fabricated thin film can not be applied as passivation layer or barrier layer of OLED.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.1
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• pp.24-28
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• 2010

We have proposed an Buffer layer to improve the transmittance of ITO. Here, $SiO_2$ and $TiO_2$ were selected as the Buffer layer coating material. The structures of Buffer layer were designed in ITO/$SiO_2/TiO_2$/Glass and ITO/Glass/$TiO_2/SiO_2$. Then, these materials were deposited by ion-assisted deposition system. Transmittances of deposited ITO were 86.14 and 85.07%, respectively. These results show that the proposed structure has higher transmittance than the conventional ITO device.

• Journal of Surface Science and Engineering
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• v.20 no.2
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• pp.49-59
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• 1987

The properties of $Cr_2O_3-Al_2O_3-SiO_2$ composite oxide coatings on steel surface were investigated. The results obtained were as follows: The microhardness of oxide coating layer increased with increasing heat-treatment temperature and $Cr_2O_3$ content in coating layer. The hardness showed the highest value (850Hv) treated at 700$^{\circ}C$ for $SiO_2:Al_2O_3:Cr_2O_3$=1:1:4. Increasing heat-treatment temperature, corrosion current density became lower and coating layer became denser. The corrosion current density showed the lowest value $(6.5{\times}10^{-5}\;Acm^2)$ treated at 750$^{\circ}C\;for\;SiO_2:Al_2O_3:Cr_2O_3$=1:1:3. These results were explained by protective layer which was formed during heat-treatment. The bonding between matrix and coating layer is expected to be made mechanically and chemically by the inter diffusion of Ni and Fe. The composite oxide coating was formed by softening of the binder with increasing heat-treatment temperature. The strengthening of coating layer is to be resulted from the dispersion of major oxide particles.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.