• 한국재료학회지
• /
• 제10권9호
• /
• pp.601-606
• /
• 2000

Ni mono-silicide는 선폭이 0.15$\mu\textrm{m}$이하에서도 전기저항이 커지는 현상이 없고 Ni와 Si이 1:1로 반응하기 때문에 얇은 실리사이드의 제조가 가능하고 도펀트의 재분포 현상을 감소시킬수 있다. 따라서 0.15$\mu\textrm{m}$급 이하 디바이스에 사용이 기대되는 NiSi의 제조를 위한 Ni 박막의 증착조건 확보와 열처리 조건에 따른 NiSi의 기초 물성조사를 수행하였다. Ni mono-silicide는 sputter의 물리적 증착방법으로 Ni 박박을 증착후 관상로를 상용하여 $150~1000^{\circ}C$ 온도 범위에서 제조하였다. 그후 SPM을 이용하여 각 시편의 표면조도를 측정하였고, 미세구조와 성분분석은 EDS가 장착된 TEM을 사용하여 측정하였다. 각 열처리 온도별 생성상의 전기적 성질은 4 point probe로 측정하였다. 본 연구의 결과, SPM은 비파괴 방법으로 NiSi가 NiSi$_2$로 변태되었는지 확인할 수 있는 효과적인 공정모니터링 방법임을 확인하였고, $800^{\circ}C$이상 공온 열처리에 잔류 Ni의 산화방지를 의해 산소분압의 제어가 $Po_2$=1.5$\pm$10(sup)-11색 이하가 되어야 함을 알 수 있었으며, 전지적 특성실험으로부터 본 연구에서 제조된 박막의 NiSi$\longrightarrow$NiSi$_2$ 상태변온도는 $700^{\circ}C$라고 판단되었다.

• 대한금속재료학회지
• /
• 제47권5호
• /
• pp.322-329
• /
• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• 공업화학
• /
• 제30권2호
• /
• pp.212-218
• /
• 2019

탄소나노튜브의 함산소불소화가 무전해 니켈도금 및 전자파 차폐효율에 미치는 영향을 확인하기 위하여, 탄소나노튜브를 산소 및 불소 혼합가스로 표면처리 후, 무전해 니켈도금을 실시하였다. 제조된 탄소나노튜브의 전자파 차폐 특성을 평가하기 위하여 폴리이미드 필름 위에 얇은 필름을 제작하였다. X-선 광전자분광법(XPS)을 이용하여 함산소불화 탄소나노튜브의 표면화학적 특성을 확인하였다. 또한, 열중량분석법(TGA)과 주사전자현미경(SEM) 분석결과, 함산소불소화 정도에 따른 탄소나노튜브의 니켈도금된 양과 표면 형상이 변화하였음을 알 수 있었다. $O_2:F_2=1:9$로 처리 후, 니켈도금된 탄소나노튜브는 1 GHz에서 약 19.4 dB 이상으로 가장 우수한 전자파 차폐효율을 나타내었다. 이러한 결과는 탄소나노튜브의 함산소불소화로 표면에 형성된 산소 및 불소 관능기 때문으로 여겨지며, 이 관능기들은 적절한 양의 니켈도금을 가능하게 하며 도금 용액에서의 분산성을 향상시켰다.

• 대한금속재료학회지
• /
• 제46권11호
• /
• pp.762-769
• /
• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.99-99
• /
• 2013

In this talk, I will present two research works in progress, which are: i) mapping of piezoelectric polarization and associated charge density distribution in the heteroepitaxial InGaN/GaN multi-quantum well (MQW) structure of a light emitting diode (LED) by using inline electron holography and ii) in-situ observation of the polarization switching process of an ferroelectric Pb(Zr1-x,Tix)O3 (PZT) thin film capacitor under an applied electric field in transmission electron microscope (TEM). In the first part, I will show that strain as well as total charge density distributions can be mapped quantitatively across all the functional layers constituting a LED, including n-type GaN, InGaN/GaN MQWs, and p-type GaN with sub-nm spatial resolution (~0.8 nm) by using inline electron holography. The experimentally obtained strain maps were verified by comparison with finite element method simulations and confirmed that not only InGaN QWs (2.5 nm in thickness) but also GaN QBs (10 nm in thickness) in the MQW structure are strained complementary to accommodate the lattice misfit strain. Because of this complementary strain of GaN QBs, the strain gradient and also (piezoelectric) polarization gradient across the MQW changes more steeply than expected, resulting in more polarization charge density at the MQW interfaces than the typically expected value from the spontaneous polarization mismatch alone. By quantitative and comparative analysis of the total charge density map with the polarization charge map, we can clarify what extent of the polarization charges are compensated by the electrons supplied from the n-doped GaN QBs. Comparison with the simulated energy band diagrams with various screening parameters show that only 60% of the net polarization charges are compensated by the electrons from the GaN QBs, which results in the internal field of ~2.0 MV cm-1 across each pair of GaN/InGaN of the MQW structure. In the second part of my talk, I will present in-situ observations of the polarization switching process of a planar Ni/PZT/SrRuO3 capacitor using TEM. We observed the preferential, but asymmetric, nucleation and forward growth of switched c-domains at the PZT/electrode interfaces arising from the built-in electric field beneath each interface. The subsequent sideways growth was inhibited by the depolarization field due to the imperfect charge compensation at the counter electrode and preexisting a-domain walls, leading to asymmetric switching. It was found that the preexisting a-domains split into fine a- and c-domains constituting a $90^{\circ}$ stripe domain pattern during the $180^{\circ}$ polarization switching process, revealing that these domains also actively participated in the out-of-plane polarization switching. The real-time observations uncovered the origin of the switching asymmetry and further clarified the importance of charged domain walls and the interfaces with electrodes in the ferroelectric switching processes.