• Journal of the Korean Ceramic Society
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• v.38 no.11
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• pp.1046-1054
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• 2001

Effects of B$_2$O$_3$and CuO addition on the microwave dielectric properties of the PbWO$_4$-TiO$_2$ceramics were investigated in order to use this material as an LTCC material for fabrication of a multilayered RF passive components module. We found that PbWO$_4$could be used as an LTCC material because of its low sintering temperature (8$50^{\circ}C$) and fairy good microwave dielectric properties($\varepsilon$$_{r}$=21.5, Q$\times$f$_{0}$=37200 GHz and $\tau$$_{f}$ =-31 ppm/$^{\circ}C$). In order to stabilize $\tau$$_{f}$ of PbWO$_4$, TiO$_2$was added to the PbWO$_4$and the mixture was sintered at 8$50^{\circ}C$. A near zero $\tau$$_{f}$ value (+0.2 ppm/$^{\circ}C$) was obtained with 8.7 mol% TiO$_2$addition. $\varepsilon$r and Q$\times$f$_{0}$ values were 22.3 and 21400 GHz, respectively. It was believed that the decrement of Q$\times$f$_{0}$ value with TiO$_2$addition was resulted from increasing grain boundary. In order to improve Q$\times$f$_{0}$, various amounts of B$_2$O$_3$and CuO were added to the 0.913PbWO$_4$-0.087TiO$_2$mixture. The optimum amount of CuO was 0.05 wt%. At this addition, the 0.913PbWO$_4$-0.087TiO$_2$ceramic showed $\varepsilon$$_{r}$=23.5, $\tau$$_{f}$ =-2.2ppm/$^{\circ}C$, and Q$\times$f$_{0}$=32900 GHz after sintered at 8$50^{\circ}C$. In case of B$_2$O$_3$addition, the optimum amount range was 1.0~2.5 wt% at which we could obtain following results; $\varepsilon$$_{r}$=20.3~22.1, Q$\times$f$_{0}$=48700~54700 GHz, and $\tau$$_{f}$ =+2.4~+8.2ppm/$^{\circ}C$.

• Macromolecular Research
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• v.14 no.6
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• pp.630-633
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• 2006

In heterojunction photovoltaic devices of $ITO/TiO_2/poly$(3-alkylthiophene)/Au, the photo current was characterized at different temperatures for different alkyl chain lengths and regioregularities: regiorandom, regioregular poly(3-hexylthiophene), and regioregular poly(3-dodecylthiophene). The regioregularity and alkyl chain length affected the photovoltaic characteristics due to differences in hole-carrier transportation. The drift charge mobilities of these devices were analyzed by the space-charge-limited current theory using the relation between the dark current and the bias voltage. The photocurrent in the devices based on poly(3-alkylthiophene)s decreased rapidly below the temperature at which the drift charge mobility was $10^{-5}\;cm^2/V{\cdot}s$.

• Journal of the Korean Ceramic Society
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• v.40 no.2
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• pp.172-177
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• 2003

Effect of glass addition on the low-temperature sintering and microwave dielectric properties of $BaTi_4O_9$-based ceramics were studied to develop the materials for the functional substrate of low-temperature co-fired ceramics. When 10 wt% of glass was added, sufficient densification was obtained and the relative density more than 98% was reached at the sintering temperature of$875{\circ}C$. The microwave dielectric properties were k=32, Q＊f=9000 GHz, ${ au}_f$=10 ppm/${\circ}C$. As the amount of glass increased, phase decompositions from $BaTi_4O_9;to;BaTi_5O_{11};and;Ba_4Ti_{13}O_{30}$ was observed.

• Journal of the Korean Ceramic Society
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• v.40 no.1
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• pp.98-103
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• 2003

The effect of glass addition on the low-temperature sintering and microwave dielectric properties in $BaO-Nd_2O_3-TiO_2$ dielectric ceramics were studied. When 10~30 wt% of alkali lithium borosilicate glass was added, the sintering temperature decreases from $1300^{\circ}C$;to;1000^{\circ}C$ and the relative density more than 95% was obtained. When the added amount of glass increased above 10 wt%, the density as well as dielectric properties changed, which was attributed to the second phase formation. When the sample was sintered at 100$0^{\circ}C$ with l0wt% of glass, the dielectric properties of $Qxf_o{ge}2800,;{varepsilon}_r{ge}65;and;{ au_f=+55 ppm/^{\circ}C$ were obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.101-102
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• 2006

금속을 도핑 함으로써 전기전도도가 향상될 것으로 생각되는 산화바나듐 나노선에 대하여 열처리 전후의 전기적 특성을 비교하였다. sol-gel 방법으로 만들어진 산화바나듐 xerogel($V_{1.66}Mo_{0.33}O_5{\cdot}nH_2O$)을 $Si_3N_4$ 절연막이 성장된 Si기판위에 분산시키고 Ti/Au으로 전극을 증착한 후 열처리 한 것과 하지 않은 두 시료의 전류-전압특성을 비교 분석하였다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.4
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• pp.179-186
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• 2019

In this study, we investigated the structural properties of $Ga_2O_3$ thin films and the photo-electrical properties of metal-semiconductor-metal (MSM) photodetectors deposited by Ti/Au electrodes. $Ga_2O_3$ thin films were grown at different temperatures using metal organic chemical vapor deposition (MOCVD). The crystal phase of $Ga_2O_3$ changed from ${\varepsilon}$-phase to ${\beta}$-phase depending on the growth temperature. The crystal structure of ${\varepsilon}-Ga_2O_3$ was confirmed by X-ray diffraction (XRD) analysis and the formation mechanism of crystal structure was discussed by scanning electron microscopy (SEM) images. From the results of current-voltage (I-V) and time-dependent photoresponse characteristics under the illumination of external lights, we confirmed that the MSM photodetector fabricated by ${\varepsilon}-Ga_2O_3$ showed much better photocurrent characteristics in the 266 nm UV range than in the visible range.

• Bulletin of the Korean Chemical Society
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• v.35 no.10
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• pp.2895-2900
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• 2014

We fabricated quantum dot-sensitized solar cells (QDSSCs) using cadmium sulfide (CdS) and cadmium telluride (CdTe) quantum dots (QDs) as sensitizers. A spin coated $TiO_2$ nanoparticle (NP) film on tin-doped indium oxide glass and sputtered Au on fluorine-doped tin oxide glass were used as photo-anode and counter electrode, respectively. CdS QDs were deposited onto the mesoporous $TiO_2$ layer by a successive ionic layer adsorption and reaction method. Pre-synthesized CdTe QDs were deposited onto a layer of CdS QDs using a direct adsorption technique. CdS/CdTe QDSSCs had high light harvesting ability compared with CdS or CdTe QDSSCs. QDSSCs incorporating single-walled carbon nanotubes (SWNTs), sprayed onto the substrate before deposition of the next layer or mixed with $TiO_2$ NPs, mostly exhibited enhanced photo cell efficiency compared with the pristine cell. In particular, a maximum rate increase of 24% was obtained with the solar cell containing a $TiO_2$ layer mixed with SWNTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.205-205
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• 2010

Recently, low temperature co-fired ceramic (LTCC) technology is widely used in sensors, actuators and microsystem fields because of its very good electrical and mechanical properties, high stability as well as possibility of making 3D micro structures. In this study, we investigated the effects of on $O_2$ annealing treatment on the electrical properties of Pb(ZrTi)$O_3$ (PZT) thin films deposited on LTCC substrate. The LTCC substrates with thickness of $400\;{\mu}m$ were fabricated by laminating 4 green tapes which consist of alumina and glass particle in an organic binder. The PZT thin films were deposited on Au / LTCC substrates by RF magnetron sputtering method. The change of the crystallization of the films were investigated under various atmosphere. The structural variation of the films were analyzed by using X-Ray diffraction (XRD) and field emission scanning electron microscopy (FESEM) and secondary ion mass spectrometry (SIMS).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.432-432
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• 2009

본 연구에서는 HW-PLD(Hot-walled Pulsed Laser Deposition) 법을 이용하여 ZnO 나노와이어를 $Al_2O_3$ 기판 위에 성장하였다. 성장된 ZnO 나노와이어는 SEM, XRD, PL 분석을 통하여 구조적 특성을 확인하였으며, 성장된 나노와이어를 photolithography 공정을 통하여 FET(Field Effect Transistor)소자를 제작하였다. 제작된 소자의 I-V 특성 측정 결과 Ti/Au 전극과 ZnO nanowire 채널 간에 ohmic 접합이 형성된 것을 확인하였으며 게이트 전압의 증가에 따라 소스와 드레인 사이의 전류가 증가하는 전형적인 n-type FET소자 특성을 나타내었다.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.