• Title/Summary/Keyword: $\mu$-controller

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Determination of Ginseng Saponins by Reversed-Phase High Performance Liquid Chromatography (역상 고속 액체크로마토그래피를 이용한 인삼 사포닌의 분석)

  • Jeong, Seung-Il;Kim, Choen-Suk;Lee, No-Woon;Choi, Kang-Ju;Lee, Yong-Gu;Kim, Il-Kwang
    • Analytical Science and Technology
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    • v.11 no.6
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    • pp.436-439
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    • 1998
  • Ginseng saponins were analysed using reversed-phase high performance liquid chromatography with several columns. The optimum conditions were as following : reverse phase column; Novapak $C_{18}$ ODS column ($3.9mm{\times}150mm$, $5{\mu}m$), acetonitrile/water binary mobile phase gradient controller system, solvent flow rate; 1.5 mL/min, and UV (203 nm) detector. The complete separation of ginsenoside $Rb_1$, $Rb_2$, Rc, Rd, Re, Rf and $Rg_1$ was achieved within 50 min. The regression coefficients of the calibration curves for seven ginsenosides were 0.98~0.99.

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Design of Digital Signal Processor for Ethernet Receiver Using TP Cable (TP 케이블을 이용하는 이더넷 수신기를 위한 디지털 신호 처리부 설계)

  • Hong, Ju-Hyung;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.8A
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    • pp.785-793
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    • 2007
  • This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

A Study on the Performance Evaluation of Antilock Brake Controller for a Heavy Vehicle (대형차량 정착용 미끄럼방지 제동장치 전자제어기의 성능평가에 관한 연구)

  • Lee, Ki-Chang;Jeon, Jung-Woo;Hwang, Don-Ha;Nam, Taek-Kun;Kim, Yong-Joo
    • Proceedings of the KIEE Conference
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    • 2003.07d
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    • pp.2025-2027
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    • 2003
  • 미끄럼방지 제동장치는 차량의 급제동 시 바퀴의 장김을 방지하여, 바퀴의 슬립을 최적으로 유지 시킴으로써 제동거리를 단축시키고, 운전자가 차량 조향성을 유지할 수 있게 만드는 차량 안정장치이다. 이 장치는 비행기의 착륙거리를 줄이기 위해 개발된 이래로, 철도 및 차량 등에도 널리 적용되고 있으며, 국내에서도 이미 승용차를 위주로 양산되고 있는 추세이다. 이러한 미끄럼방지 제동 장치는 공압 브레이크 장치를 사용하는 대형차량 분야에서는 아직 국내에서 적용된 사례가 없었으나, 지난 3 년간의 연구개발의 성과로 대형 버스에 적용 가능한 미끄럼방지 제동장치의 전자제어기가 개발 완료되었으며, 국제 규격을 바탕으로 국내 현실에 적합한 미끄럼방지 제동장치 장착 대형차량의 시험 규격을 정하여 이 규격에 의거 제동시험을 실시하고 개발 제어기의 성능을 평가하였다. 각 제동 시험은 $\mu$-Jump 제동시험 및 Split-$\mu$ 제동시험 등의 직진 주행 중 급제동시험, 급제동 중 차선변경 시험, 장애물 회피 제동시험 등을 포괄하며 국제적인 규격을 기준으로 정한 독자 규격을 만족하였다. 본 논문에서는 공압 브레이크를 장착한 대형차량의 미끄럼방지 제동장치의 제동성능평가 시험방법을 소개하고, 이 방법에 의해 성능평가 시스템 및 측정 시스템을 구성하여, 개발 전자제어기의 우수성을 확인하였으며, 그 측정결과의 일부를 제시하였다.

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A VIA-based RDMA Mechanism for High Performance PC Cluster Systems (고성능 PC 클러스터 시스템을 위한 VIA 기반 RDMA 메커니즘 구현)

  • Jung In-Hyung;Chung Sang-Hwa;Park Sejin
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.635-642
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    • 2004
  • The traditional communication protocols such as TCP/IP are not suitable for PC cluster systems because of their high software processing overhead. To eliminate this overhead, industry leaders have defined the Virtual Interface Architecture (VIA). VIA provides two different data transfer mechanisms, a traditional Send/Receive model and the Remote Direct Memory Access (RDMA) model. RDMA is extremely efficient way to reduce software overhead because it can bypass the OS and use the network interface controller (NIC) directly for communication, also bypass the CPU on the remote host. In this paper, we have implemented VIA-based RDMA mechanism in hardware. Compared to the traditional Send/Receive model, the RDMA mechanism improves latency and bandwidth. Our RDMA mechanism can also communicate without using remote CPU cycles. Our experimental results show a minimum latency of 12.5${\mu}\textrm{s}$ and a maximum bandwidth of 95.5MB/s. As a result, our RDMA mechanism allows PC cluster systems to have a high performance communication method.

Design of Highly Integrated 3-Channel DC-DC Converter Using PTWS for Wearable AMOLED (PTWS를 적용한 웨어러블 AMOLED용 고집적화 3-채널 DC-DC 변환기 설계)

  • Jeon, Seung-Ki;Lee, Hui-Jin;Choi, Ho-Yong
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.1061-1067
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    • 2019
  • In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

A Design of the High-Speed Cipher VLSI Using IDEA Algorithm (IDEA 알고리즘을 이용한 고속 암호 VLSI 설계)

  • 이행우;최광진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.64-72
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    • 2001
  • This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

Modeling and Compensatory Control of Thermal Error for the Machine Orgin of Machine Tools (공작기계 원점 열변형오차의 모델링 및 보상제어)

  • 정성종
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.8 no.4
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    • pp.19-28
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    • 1999
  • In order to control thermal deformation of the machine origin of machine tools a empirical model and a compensation system have been developed, Prior to empirical modeling the volumetric error considering shape errors and joint errors of slides is formulated through the homogeneous transformation matrix (HTM) and kinematic chain. Simulation results of the HTM method show that the thermal error of the machine origin is more critical than position-dependent errors. In order to make a stable and effective software error compensation system the GMDH (Group Method of Data Handling) models are constructed to estimate the thermal deformation of the machine origin by measuring deformation data and temperature data. A test bar and gap sensors are used to measure the deformation data. In order to compensate the estimated error the work origin shift method is developed by implementing a digital I/O interface board between a CNC controller and an IBM PC. The method shifts the work origin as much as the amounts which are calculated by the pre-established thermal error model. The experiment results for a vertical machining center show that the thermal deformation of the machine origin is reduced within $\pm$5$mu extrm{m}$.

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Optimal Design of Robust Quantitative Feedback Controllers Using Linear Programming and Genetic Algorithms

  • Bokharaie, Vaheed S.;Khaki-Sedigh, Ali
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.428-432
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    • 2003
  • Quantitative Feedback Theory (QFT) is one of most effective methods of robust controller design and can be considered as a suitable method for systems with parametric uncertainties. Particularly it allows us to obtain controllers less conservative than other methods like $H_{\infty}$ and ${\mu}$-synthesis. In QFT method, we transform all the uncertainties and desired specifications to some boundaries in Nichols chart and then we have to find the nominal loop transfer function such that satisfies the boundaries and has the minimum high frequency gain. The major drawback of the QFT method is that there is no effective and useful method for finding this nominal loop transfer function. The usual approach to this problem involves loop-shaping in the Nichols chart by manipulating the poles and zeros of the nominal loop transfer function. This process now aided by recently developed computer aided design tools proceeds by trial and error and its success often depends heavily on the experience of the loop-shaper. Thus for the novice and First time QFT user, there is a genuine need for an automatic loop-shaping tool to generate a first-cut solution. In this paper, we approach the automatic QFT loop-shaping problem by using an algorithm involving Linear Programming (LP) techniques and Genetic Algorithm (GA).

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The Design and Fabrication of RESURF type SOI n-LDMOSFET (RESURF type의 SOI n-LDMOSFET 소자 설계 및 제작)

  • Kim, Jae-Seok;Kim, Beom-Ju;Koo, Jin-Gen;Koo, Yong-Seo;An, Chul
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.355-358
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    • 2004
  • In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

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An Implementation of NMEA 0183/2000 Gateway (NMEA0183/2000 게이트웨이 구현)

  • Son, Hyeong-Gon;Joo, Moon G.;Woo, Him-Chan;Kang, Mu-Sung;Sul, Jaehoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.6
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    • pp.405-411
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    • 2017
  • As the number of sensors in a ship has increased, studies have been actively conducted to efficiently manage a large amount of data. Sensors in a ship follow the NMEA (National Marine Electronics Association) data format. In particular, NMEA0183 standardized as IEC 61162-1 and NMEA2000 standardized as IEC 61162-3 are widely used. NMEA0183 is a protocol based on serial communication and NMEA2000 is a protocol based on CAN (Controller Area Network) communication. We implemented a gateway that receives data from NMEA0183 sensors and NMEA2000 sensors and then transmits them to the server on TCP/IP network. By using the NMEA2000 0183/2000 gateway to receive the sensor data and manage it through the ship's preventive maintenance system, the sensor data can be utilized efficiently and promptly. This management can reduce crew's daily tasks and reduce the number of accidents.