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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks

  • Sung-Eun Kim (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Kwang-Il Oh (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Taewook Kang (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Sukho Lee (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Hyuk Kim (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Mi-Jeong Park (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Jae-Jin Lee (Artificial Intelligence SoC Research Division, Electronics and Telecommunications Research Institute)
  • Received : 2024.03.22
  • Accepted : 2024.08.14
  • Published : 2024.10.10
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Abstract

To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal-oxide-semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

Keywords

Acknowledgement

This work was supported by the Electronics and Telecommunications Research Institute (ETRI) grant funded by the Korea government (24ZS1230, memory-computation convergence neuromorphic computing technology).

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