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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Mixed-mode SNN crossbar array with embedded dummy switch and mid-node pre-charge scheme

  • Kwang-Il Oh (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Hyuk Kim (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Taewook Kang (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Sung-Eun Kim (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Jae-Jin Lee (AI SoC Research Division, Electronics and Telecommunications Research Institute) ;
  • Byung-Do Yang (Department of Electronics Engineering, Chungbuk National University)
  • Received : 2024.03.18
  • Accepted : 2024.08.13
  • Published : 2024.10.10
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Abstract

This paper presents a membrane computation error-minimized mixed-mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid-node pre-charge scheme to construct a high-precision current-mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28-nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 ㎼ of power consumed. Moreover, the peak-to-peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample-wise random variations.

Keywords

Acknowledgement

This study was supported by the Electronics and Telecommunications Research Institute (ETRI) grant funded by the Korean government (24ZS1230, Memory Computation Convergence Neuromorphic Computing Technology).

References

  1. Y. LeCun, Y. Bengio, and G. Hinton, Deep learning, Nature 521 (2015), no. 7553, 436-444, DOI 10.1038/nature14539.
  2. D. Wang, C. T. Lin, G. K. Chen, P. Knag, R. K. Krishnamurthy, and M. Seok, DIMC: 2219TOPS/W 2569F2/b digital in-memory computing macro in 28nm based on approximate arithmetic hardware, (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2022, pp. 266-268. DOI 10.1109/ISSCC42614.2022.9731659
  3. T. H. Hsu G. C. Chen, Y. R. Chen, R. S. Chen, C. C. Lo, K. T. Tang, M. F. Chang, and C. C. Hsieh, A 0.8V intelligent vision sensor with tiny convolutional neural network and programmable weights using mixed-mode processing-in-sensor technique for image classification. (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2022. DOI 10.1109/ISSCC42614.2022.9731675
  4. Garrett D, Park YS, Kim S, Sharma J, Huang W, Shaghaghi M, Parthasarathy V, Gibellini S, Bailey S, Moturi M, Vorenkamp P, A 1mW always-on computer vision deep learning neural decision processor, (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2023, pp. -10. DOI 10.1109/ISSCC42615.2023.10067588
  5. F. Conti, D. Rossi, G. Paulin et al., 22.1 A 12.4TOPS/W @ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing, (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2023, pp. 21-23. 10.1109/ISSCC42615.2023.10067643
  6. C. S. Thakur, J. L. Molin, G. Cauwenberghs, G. Indiveri, K. Kumar, N. Qiao, J. Schemmel, R. Wang, E. Chicca, J. Olson Hasler, J. S. Seo, S. Yu, Y. Cao, A. Van Schaik, and R. Etienne-Cummings, Large-scale neuromorphic spiking array processors: a quest to mimic the brain, Front. Neurosci. 12 (2018), 891. DOI 10.3389/fnins.2018.00891
  7. K. Roy, A. Jaiswal, and P. Panda, Towards spike-based machine intelligence with neuromorphic computing, Nature 575 (2019), no. 7784, 607-617. DOI 10.1038/s41586-019-1677-2
  8. C. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. Date, and B. Kay, Opportunities for neuromorphic computing algorithms and applications, Nat. Comput. Sci. 2 (2022), no. 1, 10-19. DOI 10.1038/s43588-021-00184-y
  9. S. Kim, S. Kim, W. Jo, S. Kim, S. Hong, and H. J. Yoo, 20.5 Ctransformer: a 2.6-18.1μJ/token homogeneous DNN-transformer/spiking-transformer processor with big-little network and implicit weight generation for large language models, (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2024, pp. 368-370. DOI 10.1109/ISSCC49657.2024.10454330
  10. M. Yang, C. H. Chien, T. Delbruck, and S. C. Liu, A 0.5V 55μW 64×2-channel binaural silicon cochlea for event-driven stereo-audio sensing, IEEE J. Solid-State Circ. 51 (2016), no. 11, 2554-2569. DOI 10.1109/JSSC.2016.2604285
  11. F. C. Bauer, D. R. Muir, and G. Indiveri, Real-time ultra-low power ECG anomaly detection using an event-driven neuromorphic processor, IEEE Trans. Biomed. Circ. Syst. 13 (2019), no. 6, 1575-1582. DOI 10.1109/TBCAS.2019.2953001
  12. I. Kiselev, C. Gao, and S. C. Liu, Spiking cochlea with systemlevel local automatic gain control, IEEE Trans. Circ. Syst. I: Regular Papers 69 (2022), no. 5, 2156-2166. DOI 10.1109/TCSI.2022.3150165
  13. B. Son, Y. Suh, S. Kim et al., 4.1 A 640×480 dynamic vision sensor with a 9μm pixel and 300Meps address-event representation (IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA), 2017, pp. 66-67. DOI 10.1109/ISSCC.2017.7870263
  14. M. Davies, A. Wild, G. Orchard, Y. Sandamirskaya, G. A. F. Guerra, P. Joshi, P. Plank, and S. R. Risbud, Advancing neuromorphic computing with Loihi: a survey of results and outlook, Proc. IEEE 109 (2021), no. 5, 911-934. DOI 10.1109/JPROC.2021.3067593
  15. P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S. K. Esser, R. Appuswamy, B. Taba, A. Amir, M. D. Flickner, W. P. Risk, R. Manohar, and D. S. Modha, A million spiking-neuron integrated circuit with a scalable communication network and interface, Sci. 345 (2014), no. 6197, 668-673. DOI 10.1126/science.1254642
  16. G. K. Chen, R. Kumar, H. E. Sumbul, P. C. Knag, and R. K. Krishnamurthy, A 4096-neuron 1M-synapse 3.8-pJ/SOP spiking neural network with on-chip STDP learning and sparse weights in 10-nm FinFET CMOS, IEEE J. Solid-State Circ. 54 (2019), no. 4, 992-1002. DOI 10.1109/JSSC.2018.2884901
  17. S. Friedmann, J. Schemmel, A. Grubl, A. Hartel, M. Hock, and K. Meier, Demonstrating hybrid learning in a flexible neuromorphic hardware system, IEEE Trans. Biomed. Circ. Syst. 11 (2017), no. 1, 128-142. DOI 10.1109/TBCAS.2016.2579164
  18. S. Moradi, N. Qiao, F. Stefanini, and G. Indiveri, A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (DYNAPs), IEEE Trans. Biomed. Circ. Syst. 12 (2018), no. 1, 106-122. DOI 10.1109/TBCAS.2017.2759700
  19. H. Cho, H. Son, K. Seong, B. Kim, H. J. Park, and J. Y. Sim, An on-chip learning neuromorphic autoencoder with currentmode transposable memory read and virtual lookup table, IEEE Trans. Biomed. Circ. Syst. 12 (2018), no. 1, 161-170. DOI 10.1109/TBCAS.2017.2762002
  20. J. Lazzaro and J. Wawrzynek, A multi-sender asynchronous extension to the AER protocol (Proc. Sixteenth Conf. on Adv. Res. in VLSI, Chapel Hill, NC, USA), 1995, pp. 158-169. DOI 10.1109/ARVLSI.1995.515618
  21. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits, 2nd. ed., Prentice Hall Press, Saddle River, NJ, USA, 2003, 107-112.
  22. J. B. Kuo and S. C. Lin, Low-voltage SOI CMOS devices and circuits, Wiley Interscience, New York, NY, USA, 2001.
  23. P. U. Diehl and M. Cook, Unsupervised learning of digit recognition using spike-timing-dependent plasticity, Front. Comput. Neurosci. 9 (2015), 99. DOI 10.3389/fncom.2015.00099