Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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A Study on the Implementation of Low-Power Cache Flushing Instructions for Persistent Memory

퍼시스턴트 메모리를 위한 저전력 캐시 플러싱 명령어 구현에 대한 연구

  • Juhee Choi (Dept. of Smart Information Communication Engineering, Sangmyung University)
  • 최주희 (상명대학교 스마트정보통신공학과)
  • Received : 2024.08.06
  • Accepted : 2024.09.12
  • Published : 2024.09.30
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Abstract

Persistent memory technology has been recognized as a next-generation memory solution because of its stability over traditional volatile memory. The primary advantage of persistent memory is its non-volatile nature, allowing data retention even when the power is off. Additionally, persistent memory offers faster read speeds compared to traditional HDDs and SSDs. However, ensuring data consistency through cache flushing commands is increasingly important so that performance and power consumption issue would be challenges. This paper proposes a new cache structure to mitigate the drawbacks of cache flushing by considering the number of flushes per cache line. On top of that, a counter and decision bit to track and manage these actions are added. As a result, this architecture decreases approximately 56% of the additional memory access.

Keywords

Acknowledgement

본 연구는 2024학년도 상명대학교 교내연구비를 지원받아 수행하였음(2024-A000-0369).

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