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SRAM-Based Area-Efficient Computing-in-Memory for AI Edge Devices

AI 엣지 디바이스를 위한 SRAM 기반 면적 효율적인 컴퓨팅 인 메모리

  • Hyun-Ki Hong ;
  • Sung-Hun Jo (Dept. of Nano & Semiconductor Engineering, Tech University of Korea)
  • 홍현기 (한국공학대학교 나노반도체공학과) ;
  • 조성훈 (한국공학대학교 나노반도체공학과)
  • Received : 2024.09.06
  • Accepted : 2024.10.12
  • Published : 2024.10.31

Abstract

In semiconductors for AI, Computing in Memory (CIM) integrates computation and memory to minimize data movement and reduce processing bottlenecks, thereby improving performance. In AI tasks that handle large amounts of data, CIM is gaining attention as a key technology that optimizes the performance of AI systems by improving power efficiency and enabling faster computation. In this paper, a new CIM architecture for AI semiconductors is proposed. The proposed architecture can perform MAC operations by controlling the width of the transistor and the pulse width of the control signal, and can be implemented in a smaller area than the existing architecture.

AI 반도체에서 Computing-in-Memory(CIM)는 연산과 저장을 통합하여 데이터 이동을 최소화하고, 병목 현상을 줄여 성능을 향상시킬 수 있다. 방대한 양의 데이터를 처리해야하는 AI 응용에서, CIM은 전력 효율을 개선하고 더 빠른 연산을 가능하게 하여 시스템의 성능을 최적화할 수 있는 핵심 기술로 주목을 받고 있다. 본 논문에서는 AI 반도체를 위한 새로운 CIM 아키텍처를 제안한다. 제안하는 아키텍처는 트랜지스터의 폭과 제어 신호의 펄스 폭을 제어하여 MAC 동작을 수행할 수 있으며 기존 아키텍처 대비 더 적은 면적으로 구현이 가능하다.

Keywords

References

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