마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제31권2호
  • /
  • Pages.16-22
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  • 2024
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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Advanced Package용 Molded Bridge Die on Substrate(MBoS) 공정 기술 연구

Research on Process Technology of Molded Bridge Die on Substrate (MBoS) for Advanced Package

  • 전재영 (하나마이크론(주)) ;
  • 김동규 (하나마이크론(주)) ;
  • 최원석 (하나마이크론(주)) ;
  • 장용규 (하나마이크론(주)) ;
  • 장상규 (하나마이크론(주)) ;
  • 고용남 (하나마이크론(주))
  • Jaeyoung Jeon (HANA Micron Ins.) ;
  • Donggyu Kim (HANA Micron Ins.) ;
  • Wonseok Choi (HANA Micron Ins.) ;
  • Yonggyu Jang (HANA Micron Ins.) ;
  • Sanggyu Jang (HANA Micron Ins.) ;
  • Yong-Nam Koh (HANA Micron Ins.)
  • 투고 : 2024.06.05
  • 심사 : 2024.06.26
  • 발행 : 2024.06.30
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초록

Artificial Intelligence(AI) 기술이 발전함에 따라 데이터 센터 분야 등에서 고사양 반도체에 대한 수요가 증가하고 있다. 이러한 추세에 맞춰 반도체 성능을 향상하기 위해 회로의 미세화 및 I/O의 고밀도화가 요구되고 있으며 이를 충족할 수 있는 기술로 차세대 packaging인 2.5dimension(D) packaging이 주목받고 있다. 2.5D packaging에 활용되는 요소 기술로는 microbump, interposer 및bridge die가 있다. 이러한 기술을 적용하면 기존 방식 대비 더 많은 수의 I/O 구현이 가능하여 동시에 다량의 정보를 송수신할 수 있으며, 전기 신호를 전달하는 배선 길이를 단축하여 전력 소모량을 감소시킬 수 있다. 본 논문에서는 molding 공정 및 R DL공정을 융합하여 제작한 Molded Bridge die on Substrate(MBoS) 공정 기술을 제안한다. 제안된 MBoS 기술은 적용이 쉽고 활용 분야가 넓어 차세대 패키징 기술의 대중화에 기여할 것으로 예상된다.

With advances of artificial intelligence (AI) technology, the demand is increasing for high-end semiconductors in various places such as data centers. In order to improve the performance of semiconductors, reducing the pitch of patterns and increasing density of I/Os are required. For this issue, 2.5dimension(D) packaging is gaining attention as a promising solution. The core technologies used in 2.5D packaging include microbump, interposer, and bridge die. These technologies enable the implementation of a larger number of I/Os than conventional methods, enabling a large amount of information to be transmitted and received simultaneously. This paper proposes the Molded Bridge die on Substrate (MBoS) process technology, which combines molding and Redistribution Layer (RDL) processes. The proposed MBoS technology is expected to contribute to the popularization of next-generation packaging technology due to its easy adaption and wide application areas.

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과제정보

이 논문은 과학기술정보통신부(원천기술개발사업)에서 시행한 PIM인공지능반도체핵심기술개발사업 지원을 받아 수행된 연구 (No. 2022M3I7A4072293)결과로 수행되었습니다.

참고문헌

  1. R. James, "The Future of the High-Performance Semiconductor Industry and Design", Proc. 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 65, 32-35 (2022).
  2. C. C. Wang, Y. C. Huang, T. K. Chang, and Y. Lin, "A new semiconductor package design flow and platform applied on high density fan-out chip", Proc. 2021 71st Electronic Components and Technology Conference (ECTC), San Diego, 112-117 (2021).
  3. P. Y. Lin, M. C. Yew, S. S. Yeh, S. M. Chen, C. H. Lin, C. S. Chen, and S. P. Jeng, "Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages", Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, 723-728 (2021).
  4. R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygun, W. L. Jen, and A. Dhall, "Embedded multidie interconnect bridge-A localized, high-density multichip packaging interconnect", IEEE Trans. Compon. Packaging Manuf. Technol., 9(10), 1952-1962 (2019).
  5. E. -C. Noh, H. -W. Lee, J. -W. Yoon, "Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging", J. Microelectron. Packag. Soc., 30(3), 1-10 (2023).
  6. M. Suh, "Technology Trends of Semiconductor Package for ESG", Journal of the Microelectronics and Packaging Society, 3(30), 35-39 (2023).
  7. A. Shehabi, et al., "United states data center energy usage report", Energy Technologies Area, Berkeley Lab, US (2016).
  8. B. Hill, "Micron Announces HBM next As Eventual Replacement for HBM2e In High-End GPUs", HotHardware, (2020) from https://hothardware.com/news/
  9. K. J. Han, "System Packaging Technology Development Trends", KIEES Magazine: Electromagnetic Technology, 31(1), 31-40 (2020).
  10. G. Duan, Y. Kanaoka, R. McRee, B. Nie, and R. Manepalli, "Die Embedding Challenges for EMIB Advanced Packaging Technology", 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1-7 (2021).
  11. R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik, "Embedded Multi-Die Interconnect Bridge (EMIB) - A High Density High Bandwidth Packaging Interconnect", 2016 IEEE 66th ECTC Conference, 557-565 (2016).
  12. A. C. Durgun, Z. Qian, K. Aygun, R. Mahajan, T. T. Hoang, and S. Y. Shumarayev, "Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration", 2019 IEEE 69th ECTC conference, 667-673 (2019).
  13. R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygun, W.-L. Jen, S. Sharan, and A. Dhall, "Embedded Multidie Interconnect Bridge - A Localized, High-Density Multichip Packaging Interconnect", IEEE Transactions on Components, Packaging, and Manufacturing Technology, 9(10), 1952-1962 (2019).
  14. H. J. Kim, J. P. Jung, "Artificial Intelligence Semiconductor and Packaging Technology Trend." J. Microelectron. Packag. Soc., 30(3), 11-19 (2023).
  15. Jiang, Feng, et al., "Wafer level warpage characterization for backside manufacturing processes of TSV interposers", 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 6897532 (2014).
  16. G. Kim, D. Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis", J. Microelectron. Packag. Soc., 25(1), 41-45 (2018).
  17. K. Kim, Y. Hwangbo, S. H. Choa, "Warpage and Solder Joint Strength of Stacked PCB using an Interposer", J. Microelectron. Packag. Soc., 30(3), 40-50 (2023).
  18. C.-C. Lee, et al., "An overview of the development of a GPU with integrated HBM on silicon interposer", 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1439-1444 (2016).