Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Novel Design of 8T Ternary SRAM for Low Power Sensor System

  • Jihyeong Yun (School of Electrical Engineering, Kyungpook National University) ;
  • Sunmean Kim (School of Electrical Engineering, Kyungpook National University)
  • Received : 2024.05.02
  • Accepted : 2024.05.30
  • Published : 2024.05.31
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Abstract

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of VDD/2 and VDD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when VDD is set to 0.9 V.

Keywords

Acknowledgement

This research was supported by the Nanomaterials Development Program through the National Research Foundation of Korea (NRF) (2022M3H4A1A04096496) funded by the Ministry of Science and ICT, Korea.

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