DOI QR코드

DOI QR Code

Co(EtCp)2프리커서를 사용한 Co 박막의 선택적 원자층 증착

Selective Atomic Layer Deposition of Co Thin Films Using Co(EtCp)2 Precursor

  • 김수정 (전남대학교 신소재공학과) ;
  • 김용태 (전남대학교 신소재공학과) ;
  • 허재영 (전남대학교 신소재공학과)
  • Sujeong Kim (Department of Materials Science and Engineering, Chonnam National University) ;
  • Yong Tae Kim (Department of Materials Science and Engineering, Chonnam National University) ;
  • Jaeyeong Heo (Department of Materials Science and Engineering, Chonnam National University)
  • 투고 : 2024.01.04
  • 심사 : 2024.01.30
  • 발행 : 2024.03.27

초록

As the limitations of Moore's Law become evident, there has been growing interest in advanced packaging technologies. Among various 3D packaging techniques, Cu-SiO2 hybrid bonding has gained attention in heterogeneous devices. However, certain issues, such as its high-temperature processing conditions and copper oxidation, can affect electrical properties and mechanical reliability. Therefore, we studied depositing only a heterometal on top of the Cu in Cu-SiO2 composite substrates to prevent copper surface oxidation and to lower bonding process temperature. The heterometal needs to be deposited as an ultra-thin layer of less than 10 nm, for copper diffusion. We established the process conditions for depositing a Co film using a Co(EtCp)2 precursor and utilizing plasma-enhanced atomic layer deposition (PEALD), which allows for precise atomic level thickness control. In addition, we attempted to use a growth inhibitor by growing a self-assembled monolayer (SAM) material, octadecyltrichlorosilane (ODTS), on a SiO2 substrate to selectively suppress the growth of Co film. We compared the growth behavior of the Co film under various PEALD process conditions and examined their selectivity based on the ODTS growth time.

키워드

과제정보

This study was financially supported by Chonnam National University (Grant number: 2023-0101-01) and the MOT IE (Ministry of Trade, Industry & Energy, 1415181061) and KSRC (Korea Semiconductor Research Consortium, 20019469) support program for the development of the future semiconductor device.

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