마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제30권3호
  • /
  • Pages.11-19
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  • 2023
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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인공지능 반도체 및 패키징 기술 동향

Artificial Intelligence Semiconductor and Packaging Technology Trend

  • 김희주 (서울시립대학교 신소재공학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • Hee Ju Kim (Department of Materials Science & Engineering, University of Seoul) ;
  • Jae Pil Jung (Department of Materials Science & Engineering, University of Seoul)
  • 투고 : 2023.08.27
  • 심사 : 2023.09.12
  • 발행 : 2023.09.30
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⟨ 이전 논문 다음 논문 ⟩

초록

최근 Chat GPT와 같은 인공지능 (Artificial Intelligence, AI) 기술의 급격한 발전에 따라 AI 반도체의 중요성이 강조되고 있다. AI 기술은 빅데이터 처리, 딥 러닝, 알고리즘 등의 요구사항으로 인해 대용량 데이터를 빠르게 처리할 수 있는 능력을 필요로 한다. 그러나 AI 반도체는 대규모 데이터를 처리하는 과정에서 과도한 전력 소비와 데이터 병목현상 문제가 발생한다. 반도체 전공정의 초미세공정이 물리적 한계에 도달함에 따라, AI 반도체의 연산을 위한 최신 패키징 기술이 요구되는 추세이다. 본 고에서는 AI 반도체에 적용가능한 인터포저, TSV, 범핑, Chiplet, 하이브리드 본딩 패키징 기술에 대해서 기술하였다. 이러한 기술들은 AI 반도체의 전력 효율과 연산 속도를 향상시키는데 기여할 것으로 기대된다.

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

키워드

과제정보

본 연구는 산업통상자원부 및 산업기술평가관리원(KEIT)의 소재부품기술개발사업 연구비 지원에 의한 연구 결과입니다(과제번호 및 과제명; '20010580', 미니LED 미세전극 접합을 위한 도전성 나노소재 기술 개발).

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