Acknowledgement
이 논문은 2023년도 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원(No. 2021R1A2C1009714, No. RS-2023-00247545)과 2023년도 정부(산업통상자원부)의 재원으로 한국산업기술진흥원의 지원(P0008458, 산업혁신인재성장지원사업)을 받아 수행된 연구임
References
- R. James, "The Future of the High-Performance Semiconductor Industry and Design", Proc. 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 65, 32-35, IEEE (2022).
- C. C. Wang, Y. C. Huang, T. K. Chang, and Y. Lin, "A new semiconductor package design flow and platform applied on high density fan-out chip", Proc. 2021 71st Electronic Components and Technology Conference (ECTC), San Diego, 112-117, IEEE (2021).
- P. Y. Lin, M. C. Yew, S. S. Yeh, S. M. Chen, C. H. Lin, C. S. Chen, and S. P. Jeng, "Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages", Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, 723-728, IEEE (2021).
- D. Liu, K. Chen, Y. Qin, Y. Zhong, Z. Wan, R. Liu, and J. Wu, "The influence of molding compound properties on system-in-package reliability for 5G application", Proc. 2021 22nd International Conference on Electronic Packaging Technology (ICEPT), Xiamen, 1-6, IEEE (2021).
- T. K. Kim, J. G. Yook, J. Y. Kim, Y. H. Cho, and U. H. Lee, "Fabrication and Characterization of Three-Dimensional Microelectromechanical System Coaxial Socket Device for Semiconductor Package Testing", Sensors, 23(14), 6350 (2023).
- R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygun, W. L. Jen, and A. Dhall, "Embedded multidie interconnect bridge-A localized, high-density multichip packaging interconnect", IEEE Trans. Compon. Packaging Manuf. Technol., 9(10), 1952-1962 (2019). https://doi.org/10.1109/TCPMT.2019.2942708
- A. R. A. Rahman, and N. A. Nayan, "Critical challenges and solutions for device miniaturization in integrated circuit packaging technology", J. Eng. Appl. Sci., 13(15), 6025-6032 (2019).
- Z. Chen, J. Zhang, S. Wang, and C. P. Wong, "Challenges and prospects for advanced packaging", Fundamental Research (2023).
- M. F. Chen, F. C. Chen, W. C. Chiou, and C. H. Doug, "System on integrated chips (SoIC (TM) for 3D heterogeneous integration", Proc. 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, 594-599, IEEE (2019).
- Z. Li, Y. Tomita, A. A. Elsherbini, P. Liu, H. A. Sawyer, J. M. Swan, and S. M. Liff, "Scaling Solder Micro-Bump Interconnect Down to 10 um Pitch for Advanced 3D IC Packages", Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, 451-456, IEEE (2021).
- H. W. Hu, and K. N. Chen, "Development of low temperature CuCu bonding and hybrid bonding for three-dimensional integrated circuits (3D IC)", Microelectron. Reliab., 127, 114412 (2021).
- K. N. Tu, and Y. Liu, "Recent advances on kinetic analysis of solder joint reactions in 3D IC packaging technology", Mater. Sci. Eng. R Rep., 136, 1-12 (2019). https://doi.org/10.1016/j.mser.2018.09.002
- K. N. Tu, H. Y. Hsiao, and C. Chen, "Transition from flip chip solder joint to 3D IC microbump: Its effect on microstructure anisotropy", Microelectron. Reliab., 53(1), 2-6 (2013). https://doi.org/10.1016/j.microrel.2012.07.029
- A. Yu, J. H. Lau, S. W. Ho, A. Kumar, W. Y. Hnin, D. Q. Yu, and D. L. Kwong, "Study of 15㎛ pitch solder microbumps for 3D IC integration", Proc. 2009 59th Electronic Components and Technology Conference (ECTC), California, 6-10, IEEE (2019).
- S. W. Yoon, J. H. Ku, N. Suthiwongsunthorn, P. C. Marimuthu, and F. Carson, "Fabrication and packaging of microbump interconnections for 3D TSV", Proc. 2009 IEEE International Conference on 3D System Integration, San Francisco, 1-5, IEEE (2009).
- S. Lee, Y. Susumago, Z. Qian, N. Takahashi, H. Kino, T. Tanaka, and T. Fukushima, "Development of 3D-IC embedded flexible hybrid system", Proc. 2019 International 3D Systems Integration Conference (3DIC), Sendai, 1-4, IEEE (2019).
- A. M. Gusak, K. N. Tu, and C. Chen, "Extremely rapid grain growth in scallop-type Cu6Sn5 during solid-liquid interdiffusion reactions in micro-bump solder joints", Scr. Mater., 179, 45-48 (2020). https://doi.org/10.1016/j.scriptamat.2020.01.005
- Y. Miwa, S. Lee, R. Liang, K. Kumahara, H. Kino, T. Fukushima, and T. Tanaka, "Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs", Proc. 2019 International 3D Systems Integration Conference (3DIC), Sendai, 1-4, IEEE (2019).
- J. Sylvestre, M. Samson, D. Langlois-Demers, and E. Duchesne, "Modeling the flip-chip wetting process", IEEE Trans. Compon. Packaging Manuf. Technol., 4(12), 2004-2017 (2014). https://doi.org/10.1109/TCPMT.2014.2364552
- M. S. Kim, W. S. Hong, and M. Kim, "Flip chip-chip scale package bonding technology with type 7 solder paste printing", JWJ, 39(4), 359-367 (2021). https://doi.org/10.5781/JWJ.2021.39.4.3
- M. Gim, C. Kim, S. Na, D. Ryu, K. Park, and J. Kim, "High-performance flip chip bonding mechanism study with laser assisted bonding" Proc. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1025-1030, IEEE (2020).
- S. B. Bulumulla, M. F. Caggiano, D. J. Lischner, and R. K. Wolf, "A comparison of large I/O flip chip and wire bonded packages", Proc. 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No. 01CH37220), Orlando, 1122-1126, IEEE (2001).
- Y. Yamaji, T. Yokoshima, N. Igawa, K. Kikuchi, H. Nakagawa, and M. Aoyagi, "A method of fabricating bump-less interconnects applicable to wafer-scale flip-chip bonding" Proc. 2008 10th Electronics Packaging Technology Conference (EPTC), Singapore, 657-662, IEEE (2008).
- B. J. Kim, G. T. Lim, J. Kim, K. Lee, Y. B. Park, and Y. C. Joo, "Intermetallic compound and Kirkendall void growth in Cu pillar bump during annealing and current stressing", Proc. 2008 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 336-340, IEEE (2008).
- G. Gao, T. Workman, L. Mirkarimi, G. Fountain, J. Theil, G. Guevara, and P. Mrozek, "Chip to wafer hybrid bonding with Cu interconnect: High volume manufacturing process compatibility study", Proc. 2019 International Wafer Level Packaging Conference (IWLPC), San Jose, 1-9, IEEE (2019).
- N. Islam, M. C. Hsieh, K. KeonTaek, and V. Pandey, "Fine pitch Cu pillar assembly challenges for advanced flip chip package", Proc. 2017 International Wafer Level Packaging Conference (IWLPC), San Fransico, 24-25, IEEE (2017).
- A. Bao, L. Zhao, Y. Sun, M. Han, G. Yeap, S. Bezuk, and K. Lee, "Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm", Proc. 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 47-49, IEEE (2014).
- P. E. GARROU, R. ASCHENBRENNER, and H. A. CHAN, "Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps", IEEE Trans. Compon. Packaging Manuf. Technol. (2004).
- A. Syed, K. Dhandapani, R. Moody, L. Nicholls, and M. Kelly, "Cu Pillar and μ-bump electromigration reliability and comparison with high pb, SnPb, and SnAg bumps", Proc. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 332-339, IEEE (2011).
- J. C. Lin, Y. Qin, and J. Woertink, "Investigation of the Growth of Intermetallic Compounds Between Cu Pillars and Solder Caps", J. Electron. Mater., 43, 4134-4145 (2014). https://doi.org/10.1007/s11664-014-3318-8
- H. Y. Hsiao, A. D. Trigg, and T. C. Chai, "Failure mechanism for fine pitch microbump in Cu/Sn/Cu system during current stressing", IEEE Trans. Compon. Packaging Manuf. Technol., 5(3), 314-319 (2015). https://doi.org/10.1109/TCPMT.2015.2398416
- N. Lay, N. DiNapoli, K. Rahim, S. Razmyar, and M. Holliday, "Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5/3D Advanced Packaging", IMAP-Source Proceedings, 2022(1), 273-279 (2023). https://doi.org/10.4071/001c.74770
- Y. Wang, I. M. De Rosa, and K. N. Tu, "Size effect on ductileto-brittle transition in Cu-solder-Cu micro-joints", Proc. 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, 632-639, IEEE (2015).
- L. M. Yin, X. P. Zhang, and C. Lu, "Size and volume effects on the strength of microscale lead-free solder joints", J. Electron. Mater., 38(10), 2179-2183 (2009). https://doi.org/10.1007/s11664-009-0858-4
- C. J. Hang, C. Q. Wang, M. Mayer, Y. H. Tian, Y. Zhou, and H. H. Wang, "Growth behavior of Cu/Al intermetallic compounds and cracks in copper ball bonds during isothermal aging", Microelectron. Reliab., 48(3), 416-424 (2008). https://doi.org/10.1016/j.microrel.2007.06.008
- F. Song, and S. R. Lee, "Investigation of IMC thickness effect on the lead-free solder ball attachment strength: comparison between ball shear test and cold bump pull test results", Proc. 56th Electronic Components and Technology Conference (ECTC), San Diego, 8, IEEE (2006).
- L. Liu, and M. Huang, "Effect of solder volume on interfacial reactions between sn3. 5ag0. 75cu solder balls and cu pad", Proc. 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Xi'an, 299-304, IEEE (2010).
- Y. S. Park, J. T. Moon, Y. W. Lee, J. H. Lee, and K. W. Paik, "Effect of fine solder ball diameters on intermetallic growth of Sn-Ag-Cu solder at Cu and Ni pad finish interfaces during thermal aging", Proc. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1870-1877, IEEE (2011).
- J. W. Yoon, B. I. Noh, J. H. Yoon, H. B. Kang, and S. B. Jung, "Sequential interfacial intermetallic compound formation of Cu6Sn5 and Ni3Sn4 between Sn-Ag-Cu solder and ENEPIG substrate during a reflow process", J. Alloys Compd., 509(9), L153-L156 (2011). https://doi.org/10.1016/j.jallcom.2011.01.015
- J. W. Yoon, B. I. Noh, and S. B. Jung, "Comparative study of ENIG and ENEPIG as surface finishes for a Sn-Ag-Cu solder joint", J. Electron. Mater., 40, 1950-1955 (2011). https://doi.org/10.1007/s11664-011-1686-x
- J. E. Yu, S. J. Kim, W. S. Hong, and N. H. Kang, "Intermetallic compound growth induced by electromigration in Sn-2.5 ag solder joints with ENEPIG surface finish", JWJ, 40(3), 225-232 (2022). https://doi.org/10.5781/JWJ.2022.40.3.3
- N. Chang, C. K. Chung, Y. P. Wang, C. F. Lin, P. J. Su, T. Shih, and J. Hung, "3D micro bump interface enabling top die interconnect to true circuit through silicon via wafer", Proc. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1888-1893, IEEE (2020).
- C. Y. Ho, "Effects of self-aligned electroplating Cu pillar/SnxAg bump on dense Al lines for chip-to-package connection", Mater. Sci. Semicond, 49, 1-7 (2016). https://doi.org/10.1016/j.mssp.2016.02.020
- A. Cassier, L. Zhao, A. Syed, S. Bezuk, W. Miller, A. Leong, and M. Slessor, "Reliable Testing of Cu Pillar Technology for Smart Devices", Chip Scale Review, 18(5), 22-27 (2014).
- Y. A. Shen, and C. Chen, "Study of grain size and orientation of 30 ㎛ solder microbumps bonded by thermal compression", Proc. 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, 204-206, IEEE (2015).
- Y. J. Chen, C. K. Chung, C. R. Yang, and C. R. Kao, "Single-joint shear strength of micro Cu pillar solder bumps with different amounts of intermetallics", Microelectron. Reliab., 53(1), 47-52 (2013). https://doi.org/10.1016/j.microrel.2012.06.116
- B. H. Kwak, M. H. Jeong, J. W. Kim, B. Lee, H. J. Lee, and Y. B. Park, "Correlations between interfacial reactions and bonding strengths of Cu/Sn/Cu pillar bump", Microelectron. Eng., 89, 65-69 (2012). https://doi.org/10.1016/j.mee.2011.01.020
- B. J. Kim, G. T. Lim, J. Kim, K. Lee, Y. B. Park, H. Y. Lee, and Y. C. Joo, "Intermetallic compound growth and reliability of Cu pillar bumps under current stressing", J. Electron. Mater., 39, 2281-2285 (2010). https://doi.org/10.1007/s11664-010-1324-z
- C. Tang, W. Zhu, L. Wang, and G. Li, "A Study on the Joint Properties and Reliability of 25㎛ Cu/Ni/Sn-3.5 Ag Bonding Process with Chip on Chip Thermal Compression Bonding", Proc. 2020 21st International Conference on Electronic Packaging Technology (ICEPT), Guangzhou, 1-4, IEEE (2020).
- M. S. Kim, M. S. Kang, J. H. Bang, C. W. Lee, M. S. Kim, and S. Yoo, "Interfacial reactions of fine-pitch Cu/Sn-3.5 Ag pillar joints on Cu/Zn and Cu/Ni under bump metallurgies", J. Alloys Compd., 616, 394-400 (2014). https://doi.org/10.1016/j.jallcom.2014.07.124
- Y. B. Park, G. T. Park, B. R. Lee, J. B. Kim, and K. Son, "Solder Volume Effect on Electromigration Failure Mechanism of Cu/Ni/Sn-Ag Microbumps", IEEE Trans. Compon. Packaging Manuf. Technol., 10(10), 1589-1593 (2020). https://doi.org/10.1109/TCPMT.2020.3005644
- C. Y. Na, B. M. Jeon, J. W. Kim, W. S. Jung, J. S. Jeong, S. M. Cho, and H. S. Park, "Fabrication of 30 ㎛ Sn Microbumps by Electroplating and Investigation of IMC Characteristics on Shear Strength", Electronics, 12(1), 144 (2020).
- M. Li, D. W. Kim, S. Gu, D. Y. Parkinson, H. Barnard, and K. N. Tu, "Joule heating induced thermomigration failure in un-powered microbumps due to thermal crosstalk in 2.5 D IC technology", J. Appl. Phys., 120(7) (2016).
- H. K. Cheng, Y. J. Lin, C. M. Chen, K. C. Liu, Y. L. Wang, and T. F. Liu, "Microstructural evolution of Cu/solder/Cu pillar-type structures with different diffusion barriers", Metall. Mater. Trans., 47, 3971-3980 (2016). https://doi.org/10.1007/s11661-016-3591-7
- B. Lee, H. Jeon, K. W. Kwon, and H. J. Lee, "Employment of a bi-layer of Ni (P)/Cu as a diffusion barrier in a Cu/Sn/Cu bonding structure for three-dimensional interconnects", Acta Mater., 61(18), 6736-6742 (2013). https://doi.org/10.1016/j.actamat.2013.07.043