한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제26권8호
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  • Pages.1142-1147
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  • 2022
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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소벨 연산을 이용한 FPGA 기반 고속 윤곽선 검출 회로 구현

FPGA-based Implementation of Fast Edge Detection using Sobel Operator

  • Ryu, Sang-Moon (Department of Information and Control Engineering, Kunsan National University)
  • 투고 : 2022.07.05
  • 심사 : 2022.07.20
  • 발행 : 2022.08.31
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⟨ 이전 논문 다음 논문 ⟩

초록

영상에 포함된 객체의 인식을 위해서는 영상에 대한 윤곽선 검출이 선행되어야 한다. 윤곽선 검출 연산이 하드웨어로 수행되면 그 수행 시간이 소프트웨어로 구현된 경우보다 비교할 수 없을 만큼 감소하게 된다. 윤곽선 검출을 위한 연산 중 하드웨어 구현에 적합한 연산은 소벨 연산이며, 소벨 연산을 효율적으로 FPGA로 구현하기 위한 많은 연구가 수행되었다. 본 논문에서는 소벨 연산을 FPGA로 구현하기 위한 기존의 구조를 개선하여, 약간의 추가적인 하드웨어 자원의 사용만으로 그 성능을 개선할 수 있는 회로 구조를 제안한다. 제안된 구조는 윤곽선 검출 대상 영상이 메모리에 저장되어 있는 경우에 적합하며 기존의 방법 대비 약 2배의 성능 향상을 이룰 수 있다.

The edges of image should be detected first so that the objects in the image can be identified. An hardware-implemented edge detection algorithm outperforms its software version. Sobel operation is the most suitable algorithm for an hardware implementation of edge detection. And lots of works have been done to perform Sobel operations efficiently on FPGA-based hardware. This work proposes how to implement fast edge detection circuit on FPGA, which is based on the conventional circuit for edge detection using Sobel operator. The newly proposed circuit is suitable for processing images when the images are stored in memory devices and outperforms the conventional one with little additional FPGA resources. Both the conventional circuit and the proposed circuit were implemented on an FPGA. And the result showed that the proposed circuit almost doubles the performance in processing images and needs little additional FPGA resources.

키워드

참고문헌

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