정보처리학회논문지:컴퓨터 및 통신 시스템 (KIPS Transactions on Computer and Communication Systems)

  • 제11권1호
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  • Pages.1-8
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  • 2022
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  • 2287-5891(pISSN)
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  • 2734-049X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
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FPGA를 이용한 32-Bit RISC-V 프로세서 설계 및 평가

Design and Evaluation of 32-Bit RISC-V Processor Using FPGA

  • 투고 : 2021.09.28
  • 심사 : 2021.11.22
  • 발행 : 2022.01.31
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⟨ 이전 논문 다음 논문 ⟩

초록

RISC-V는 오픈 소스 명령어 집합 구조로, 간단한 기본 구조를 가지며 목적에 따라 명령어 집합을 유연하게 확장할 수 있다. 본 논문에서는 소형, 저전력 32-bit RISC-V 프로세서를 설계하여 RISC-V 임베디드 시스템 연구를 위한 기반을 마련하고자 하였다. 설계한 프로세서는 2단계 파이프라인으로 구성하였고, RISC-V ISA 중 FENCE, EBREAK 명령어를 제외한 32-bit 정수형 ISA 및 인터럽트 처리를 위한 특권 ISA를 지원한다. Vivado Design Suite를 이용하여 합성한 결과 Xilinx Zynq-7000 FPGA에서 1895개의 LUT 및 1195개의 플립플롭을 사용하였고, 0.001W의 전력을 소모하였다. 이를 GPIO, UART, 타이머와 함께 시스템을 구성하여 합성하였고, FPGA 상에서 FreeRTOS를 포팅하여 16MHz에서의 동작을 검증하였다. Dhrystone, Coremark 벤치마크를 통해 성능을 측정하여 목적에 따라 확장 가능한 저전력 고효율 프로세서임을 보였다.

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

키워드

과제정보

본 연구는 삼성전자의 지원(과제번호IO210204-08384-02)을 받아 수행된 결과임. 이 성과는 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원을 받아 수행된 연구임(NRF-2019R1A2C1088390).

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