반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
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TSV 디자인 요인에 따른 기생 커패시턴스 분석

Parasitic Capacitance Analysis with TSV Design Factors

  • 서성원 (강남대학교 전자패키지연구소) ;
  • 박정래 (강남대학교 전자패키지연구소) ;
  • 김구성 (강남대학교 전자패키지연구소)
  • Seo, Seong-Won (Electronic Packaging Research Center, Kangnam University) ;
  • Park, Jung-Rae (Electronic Packaging Research Center, Kangnam University) ;
  • Kim, Gu-Sung (Electronic Packaging Research Center, Kangnam University)
  • 투고 : 2022.11.09
  • 심사 : 2022.12.14
  • 발행 : 2022.12.31
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초록

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

키워드

과제정보

이 연구는 2022년도 산업통상자원부 및 산업기술평가관리원(KEIT) 연구비 지원에 의한 연구임('P0008458')

참고문헌

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