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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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An efficient reliability estimation method for CNTFET-based logic circuits

  • Jahanirad, Hadi (Department of Electrical Engineering, University of Kurdistan) ;
  • Hosseini, Mostafa (Department of Electrical Engineering, University of Kurdistan)
  • Received : 2019.12.17
  • Accepted : 2020.11.03
  • Published : 2021.08.01
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Abstract

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

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References

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