International Journal of Internet, Broadcasting and Communication

  • 제13권3호
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  • Pages.104-108
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  • 2021
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  • 2288-4920(pISSN)
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  • 2288-4939(eISSN)
한국인터넷방송통신학회 (The Institute of Internet, Broadcasting and Communication)
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A Technique for Improving the Performance of Cache Memories

  • Cho, Doosan (Department of Electrical & Electronic Engineering, Sunchon National Univ.)
  • 투고 : 2021.06.25
  • 심사 : 2021.07.03
  • 발행 : 2021.08.31
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초록

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

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과제정보

This work was supported by a research promotion program of SCNU.

참고문헌

  1. D. Cho, "A Study on Improvement of Low-power Memory Architecture in IoT/edge Computing", Journal of the Korean Society of Industry Convergence, Vol. 24, No. 1, pp. 69-77, Feb. 2021. DOI: https://doi.org/10.21289/KSIC.2021.24.1.69
  2. J. Cho, J. Lee, D. Cho, "Efficient memory design for medical database", Basic & Clinical Pharmacology & Toxicology, Vol. 125, pp. 198, July. 2019.
  3. J. Cho, JM Youn, D. Cho, "An Automatic Array Distribution Technique for Multi-Bank Memory of High Performance IoT Systems", World, Vol. 3, No. 1, pp. 15-20, Nov. 2019. DOI: https://gvpress.com/journals/WJWDE/vol3_no1/vol3_no1_2019_03.html
  4. D. Cho, "Study on Memory Performance Improvement based on Machine Learning", The Journal of the Convergence on Culture Technology, Vol. 7, No. 1, pp. 615-619, Feb. 2021. DOI: https://doi.org/10.17703/JCCT.2021.7.1.615
  5. D. Cho, "Memory Design for Artificial Intelligence", International Journal of Internet, Broadcasting and Communication, Vol. 12, No. 1, pp. 90-94, Dec. 2020. DOI: https://doi.org/10.7236/IJIBC.2020.12.1.90
  6. J. Yoon, D. Cho, "A spill data aware memory assignment technique for improving power consumption of multimedia memory systems", Multimedia Tools and Applications, Vol. 78, No. 5, pp. 5463-5478, Mar. 2019. DOI: https://doi.org/10.1007/s11042-018-6783-x
  7. J. Cho,, J. Lee, D. Cho, "Low-End Memory Subsystem Optimization Process", International Journal of Smart Home, Vol. 13, No. 2, pp. 11-16, Oct. 2019. DOI: http://dx.doi.org/10.21742/ijsh.2019.13.2.02
  8. J. Cho, D. Cho,, Y. Kim "Study on LLVM application in Parallel Computing System", The Journal of the Convergence on Culture Technology, Vol. 5, No. 1, pp. 395-399, Feb. 2019. DOI: http://dx.doi.org/10.17703/JCCT.2019.5.1.395
  9. J. Cho, D. Cho, "Development of a Prototyping Tool for New Memory Subsystem", International Journal of Internet, Broadcasting and Communication, Vol. 11, No. 1, pp. 69-74, Jan. 2019. DOI: http://dx.doi.org/10.7236/IJIBC.2019.11.1.69