과제정보
이 연구는 2020년도 산업통상자원부 및 산업기술평가관리원(KEIT) 연구비 지원에 의한 연구임('20010170').
참고문헌
- H. Jun et al., "HBM (High Band wid th Memory) DRAM Technology and Architecture," 2017 IEEE International Memory Workshop (IMW), 1-4 (2017).
- P. Holzinger, D. Reiser, T. Hahn and M. Reichenbach, "Fast HBM Access with FPGAs: Analysis, Architectures, and Applications," 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 152-159 (2021)
- JEDEC Standard High Bandwidth Memory (HBM) DRAM Specification JESD235 2013.
- V. S. Rao et al., "TSV interposer fabrication for 3D IC packaging," 2009 11th Electronics Packaging Technology Conference, 431-437 (2019)
- J. H. Lau, "Overview and outlook of through-silicon via (TSV) and 3D integrations", Microelectron. Int., 28(2), 8-22 (2011) https://doi.org/10.1108/13565361111127304
- T. S. Yoon, T. S. Kim, "Thermo-Mechanical Reliability of TSV based 3D-IC", J. Microelectron. Packag. Soc., 24(1), 35-43 (2017) https://doi.org/10.6117/KMEPS.2017.24.1.035
- D. U. Lee et al., "22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 334-336 (2020)
- C. Oh et al., "22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), 330-332 (2020)
- K. Hara, N. Hashimoto, H. Ito, et al. Active Si Interposer : Combination of Through-Si Vias and Redistribution. MRS Online Proceedings Library 970, 503 (2006).
- H. J. Lau, 3D IC Integration and Packaging, pp. 11, McGraw-Hill Education (2016).