Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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Analysis of Reel Tape Packing process conditions using DOE

실험계획법을 이용한 Reel Tape Packaging 공정조건 분석

  • Kim, Jae Kyung (Industrial Technology Research Institute, Kongju National University) ;
  • Na, Seung Jun (Graduate School of Mechanical Engineering, Kongju National University) ;
  • Kwon, Jun Hwan (Graduate School of Mechanical Engineering, Kongju National University) ;
  • Jeon, Euy Sik (Industrial Technology Research Institute, Kongju National University)
  • 김재경 (공주대학교 생산기술연구소) ;
  • 나승준 (공주대학교 대학원 기계공학과) ;
  • 권준환 (공주대학교 대학원 기계공학과) ;
  • 전의식 (공주대학교 생산기술연구소)
  • Received : 2020.06.26
  • Accepted : 2020.06.26
  • Published : 2020.06.30
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Abstract

Today's placement machines can pick and place thousands of components per hour with a very high degree of accuracy. The packaged semiconductor chips are inserted into a carrier at regular intervals, covered with a tape to protect the chips from external impact, and supplied in a roll form. These packaging processes also progress rapidly in a consistent direction, affecting the peelback strength between the cover tape and carrier depending on the main process conditions. In this paper, we analyzed the main process variables that affect peelback strength in the reel tape packaging process for packaging semiconductor chips. The main effects and interactions were analyzed. The peelback strength range required in the packaging process was set as the nominal the best characteristics, and the optimum process condition satisfying this was derived.

Keywords

References

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