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Low-area Bit-parallel Systolic Array for Multiplication and Square over Finite Fields

  • Kim, Keewon (Dept. of Applied Computer Engineering, Dankook University)
  • Received : 2020.01.15
  • Accepted : 2020.02.07
  • Published : 2020.02.28

Abstract

In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim's systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.

본 논문은 유한체상의 곱셈과 제곱을 동시에 실행 가능한 알고리즘에서 공통적인 연산 부분을 도출하고, 순차적인 처리를 통해서 하드웨어를 감소시키고 공간면에서 효율적인 비트-병렬 시스톨릭 어레이를 제안한다. 제안한 시스톨릭 어레이는 기존의 어레이에 비해 적은 공간 및 공간-시간 복잡도(area-time complexity)를 가진다. 기존의 구조들과 비교하면, 제안한 시스톨릭 어레이는 공간 복잡도면에서 Choi-Lee, Kim-Kim의 시스톨릭 어레이의 약 48%, 44% 감소되었으며, 공간-시간 복잡도면에서 약 74%, 44% 가량 감소되었다. 따라서 제안한 시스톨릭 어레이는 VLSI 구현에 적합하며 사물인터넷과 같이 하드웨어 제약이 있는 환경에서 기초적인 구성 요소로 적용할 수 있다.

Keywords

References

  1. A. J. Menezes, P.C. van Oorschot, S.A. Vanstone, "Handbook of Applied Cryptography" Boca Raton, FL, CRC Press, 1996.
  2. R. Lidl, H. Niederreiter, "Introduction to Finite Fields and Their Applications" New York, Cambridge University Press, 1994.
  3. W. T. Huang, C. H. Chang, C. W. Chiou, F. H. Chou, "Concurrent Error Detection and Correction in a Polynomial Basis Multiplier over GF($2^m$)," IET Inf. Secur., Vol. 4, No. 3, pp. 111-124, Sep. 2010. DOI: 10.1049/iet-ifs.2009.0160
  4. K. W. Kim, S. H. Kim, "A Low Latency Semi-systolic Multiplier over GF($2^m$)," IEICE Electron. Express, Vol. 10, No. 13, pp. 20130354, July 2013. DOI: 10.1587/elex.10.20130354
  5. K. W. Kim, J. C. Jeon, "A Semi-systolic Montgomery Multiplier over GF($2^m$)," IEICE Electonics Express, Vol. 12, No. 21, pp. 20150769, Nov. 2015. DOI: 10.1587/elex.12.20150769
  6. K. W. Kim, S. C. Han, "Low Latency Systolic Multiplier over GF($2^m$) Using Irreducible AOP," IEMEK J. Embed. Sys. Appl., Vol. 11, No. 4, pp. 227-233, Aug. 2016. DOI: 10.14372/IEMEK.2016.11.4.227
  7. S. H. Choi, K. J. Lee, "Low Complexity Semi-systolic Multiplication Architecture over GF($2^m$)," IEICE Electron. Express, Vol. 11, No. 20, pp. 20140713, Oct. 2014. DOI: 10.1587/elex.11.20140713
  8. K. W. Kim, "Low-latency Semi-systolic Architecture for Multiplication over Finite Fields," IEICE Electron. Express, Vol. 16, No. 10, pp. 20190080, Apr. 2019. DOI: 10.1587/elex.16.20190080
  9. S. W. Wei, "A Systolic Power-sum Circuit for GF($2^m$)," IEEE Transactions on Computers, Vol. 43, No. 2, pp. 226-229, Feb. 1994. DOI: 10.1109/12.262128
  10. C. L. Wang, J. H. Guo, "New Systolic Arrays for C+$AB^2$, Inversion, and Division in GF($2^m$)," IEEE Transactions on Computers, Vol. 49, No. 10, pp. 1120-1125, Oct. 2000. DOI: 10.1109/12.888047
  11. K. W. Kim, W. J. Lee, "Low-complexity Parallel and Serial Systolic Architectures for $AB^2$ Multiplication in GF($2^m$)," IETE Technical Review, Vol. 30, No. 2, pp. 134-141, Mar. 2013. DOI: 10.4103/0256-4602.110552
  12. S. H. Choi, K. J. Lee, "Parallel in/out Systolic $AB^2$ Architecture with Low Complexity in GF($2^m$)," Electron. Lett., Vol. 52, No. 13, pp. 1138-1140, Jun. 2016. DOI: 10.1049/el.2015.3681
  13. T. W. Kim, K. W. Kim, "Low-latency Montgomery $AB^2$ Multiplier Using Redundant Representation over GF($2^m$)," IEMEK Journal of Embedded Systems and Applications, Vol. 12, No. 1, pp. 11-18, Feb. 2017. DOI: 10.14372/IEMEK.2017.12.1.11
  14. P. A. Scott, S. J. Simmons, S. E. Tavares, L. E. Peppard, "Architectures for Exponentiation in GF($2^m$)," IEEE J. Sel. Areas Commun. Vol. 6, No. 3, pp. 578-585, Apr. 1988, DOI: 10.1109/49.1927
  15. K. J. Lee, K. Y. Yoo, "Linear Systolic Multiplier/squarer for Fast Exponentiation," Inf. Process. Lett. Vol. 76, No. 3, pp. 105-111, Dec. 2000, DOI: 10.1016/S0020-0190(00)00131-9
  16. J. C. Ha, S. J. Moon, "A Common-multiplicand Method to the Montgomery Algorithm for Speeding up Exponentiation," Inf. Process. Lett. Vol. 66, No. 2, pp. 105-107, Apr. 1998, DOI:10.1016/S0020-0190(98)00031-3
  17. S. H. Choi, K. J. Lee, "Efficient Systolic Modular Multiplier/squarer for Fast Exponentiation over GF($2^m$)," IEICE Electron. Express, Vol. 12, No. 11, pp. 20150222, May 2015. DOI: 10.1587/elex.12.20150222
  18. K. W. Kim, J. D. Lee, "Efficient Unified Semi-systolic Arrays for Multiplication and Squaring over GF($2^m$)," IEICE Electron. Express, Vol. 14, No. 12, pp. 20170458, 2017. DOI: 10.1587/elex.14.20170458
  19. K. W. Kim, H. H. Lee, S. H. Kim, "Efficient Combined Algorithm for Multiplication and Squaring for Fast Exponentiation over Finite Fields GF($2^m$)," Proceedings of the 7th International Conference on Emerging Databases, LNEE 461, pp. 50-57, Aug. 2017. DOI: 10.1007/978-981-10-6520-0
  20. K. W. Kim, S. H. Kim, "Efficient Bit-parallel Systolic Architecture for Multiplication and Squaring over GF($2^m$)," IEICE Electron. Express, Vol. 15, No. 2, pp. 20171195, 2018. DOI: 10.1587/elex.14.20171195
  21. D. E. Knuth, "The Art of Computer Programming, Seminumerical Algorithms, Vol. II," Addison-Wesley, MA, 1997.