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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Array pattern synthesis using semidefinite programming and a bisection method

  • Lee, Jong-Ho (School of Electronic Engineering, Soongsil University) ;
  • Choi, Jeongsik (Intel Labs, Intel Corporation) ;
  • Lee, Woong-Hee (Department of Communication Systems, KTH Royal Institute of Technology) ;
  • Song, Jiho (School of Electrical Engineering, University of Ulsan)
  • Received : 2018.08.16
  • Accepted : 2018.12.10
  • Published : 2019.10.01
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Abstract

In this paper, we propose an array pattern synthesis scheme using semidefinite programming (SDP) under array excitation power constraints. When an array pattern synthesis problem is formulated as an SDP problem, it is known that an additional rank-one constraint is generated inevitably and relaxed via semidefinite relaxation. If the solution to the relaxed SDP problem is not of rank one, then conventional SDP-based array pattern synthesis approaches fail to obtain optimal solutions because the additional rank-one constraint is not handled appropriately. To overcome this drawback, we adopted a bisection technique combined with a penalty function method. Numerical applications are presented to demonstrate the validity of the proposed scheme.

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References

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