ZVT Series Capacitor Interleaved Buck Converter with High Step-Down Conversion Ratio

Abstract

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.

I. INTRODUCTION

The step-down power-conversion technique is widely used in the power sources for microprocessors, automotive applications, LED drivers, solar-power regulators and so on. In the field of power conversion, high efficiency and high power density of power converters are the ultimate goal of researchers and engineers. However, owing to the high voltage stress and current stress of the components in power conversion systems, there are large conduction losses of the components, switching losses of the power switches, reverse-recovery switching losses of the power diodes and so on. These losses limit the efficiency improvements of power converters. In order to improve the power conversion efficiency of DC-DC step-down converters, passive snubbers were presented in [1], [2] to achieve zero-current turn-on and zero-voltage turn-off of switches. As a result, the switching losses of the power switches can be reduced. In addition, the coupled-inductor technique is introduced to the output-side of a step-down converter to relieve the reverse-recovery problems of output diodes in [3]-[5]. However, such a technique is achieved at the expense of increased voltage or current stress on the main switches. Thus, the improved performance of this converter is limited. In [6], a twin-buck converter with zero voltage transition was proposed. However, the soft switching ranges of this converter are narrowed which is determined by the restored inductor energy. By introducing a coupled-inductor and auxiliary switch, efficient ZVS operation with load variations of the converter was obtained in [7]. However, the circuit complexity of the proposed converter is increased. When operating in the critical conduction mode, soft switching for the main switches and diode in the buck converter is achieved. In addition, Gallium nitride (GaN) power switching devices [8] can be used to further improve the efficiency of the buck converter. Unfortunately, a large current ripple increases the conduction losses of the power switches and diode [9]. Thus, it is only available for low power applications. In [10], [11], the switch voltage stress of a converter was reduced by utilizing the switch-capacitor technique. Thus, a low switching loss and improved step-down conversion ratio are achieved to improve the character of this converter. A soft switching cell [12] and an active clamp circuit [13] can be used in the buck converters in PV panel and wind turbines applications. The zero voltage transition technique was first presented by Guichao Hua et al. [14] in order to achieve zero voltage switching of power switches without increasing the voltage stress and current stress in PWM converters. When this technique is applied in DC/DC buck converters and interleave buck converters [15]-[20], their efficiency can be increased.

In many applications, a high step-down conversion ratio is required to prevent the converter from operating at an extreme duty cycle. Many techniques have been presented to solve this problem. Four-phase interleaved buck converters [21], [22] and a two phase interleave buck converter [23] were proposed to achieve a high step-down conversion ratio and low switch voltage stress. In addition, automatic current sharing is also achieved without adding any active auxiliary components or using transformers. A series capacitor buck converter was proposed in [24] to reduce switching losses and inductor current ripple. Only one capacitor is added to the traditional interleave buck converter. Thus, the efficiency of interleave buck converters can be improved with a simple circuit topology. In order to further extended the duty cycle, the coupled-inductor technique was utilized in a converter in [25] by regulating the turns-ratio of the couple-inductor and the duty cycle of the main switches. In [26], two series capacitors have been introduced to an interleaved buck converter to achieve a very high step-down conversion ratio. By combining a quadratic buck converter and the soft switching technique, a high step-down ratio and zero voltage switching for the main switches can be achieved. As a result, this converter has been successfully applied to high step-down ratio applications [27], [28]. However, in terms of the cascade of the power conversion in quadratic buck converters, the efficiency is very low despite utilizing the soft switching technique. A three-level buck converter is presented to reduce the switch voltage stress of converters and a zero current transition technique is utilized to reduce switching losses. Thus, a high efficiency can be obtained. However, floating four switches are used in the converter proposed in [29]. However, the control of this converter is very complex. A zero voltage transition technique is utilized in the fourth-order buck converter [30], and high step-down and ZVS of the main switches can be achieved. However, this buck converter topology is also complex.

In order to achieve a high efficiency and a high step-down conversion ratio, a zero voltage transition technique is introduced to the series capacitor interleaved buck converter in this paper. The proposed converter, where the ZCS-ZVS PWM circuit cell [31], [32] is composed of a series connection of auxiliary switches and an inductor, is utilized. Zero voltage transition of the main power switches can be achieved and zero current switching of the auxiliary switches can be obtained in a wide operating range. Due to the small operating time of the auxiliary circuit, the additional conduction losses caused by the auxiliary circuit are very small. The proposed technique does not increase the voltage stress and current stress of the main switches and diodes. It behaves as a PWM-type character.

The circuit configuration and operation principle of the proposed converter are presented in Section II. Relevant analysis results, including the voltage transfer gain, soft switching condition, selection of the auxiliary circuit parameters and implementation of the driver circuit, are given in Section III. A loss analysis of the proposed converter is shown in Section IV, and the performance of the proposed converter is confirmed by the experimental results obtained with a 100V/10V prototype in Section V. Topology variations of the proposed converter are illustrated in Section VI, and some conclusions are given in Section VII.

II. PROPOSED ZVT SERIES CAPACITOR INTERLEAVED BUCK CONVERTER

A. Circuit Configuration

The proposed zero voltage transition (ZVT) series capacitor based interleaved buck converter topology is shown in Fig. 1. The series capacitor based interleaved buck converter is composed of the switches S₁ and S₂, the diodes D₁ and D₂, the output inductors L₁ and L₂, and the series capacitor C₁, which was proposed and analyzed by Il-Oun Lee, et al. [24]. The analyzed results show that series capacitor interleaved buck converters have the merits of extended duty cycle, reduced switching losses, decreased inductor current ripples, and automatic current balancing, when compared with the interleaved buck converter. Therefore, the series capacitor interleaved buck converter has been as potential candidate in applications where non-isolation, a high step-down conversion ratio and a high output current with low ripple are required. However, the switching losses and the capacitive discharging losses of the power switches in series capacitor buck converters are the dominant losses as derived from a loss analysis of this converter. These problems become worse with an increase in the switching frequency. Thus, in order to further improve the efficiency of this converter, the switching losses and capacitive discharging losses should be reduced or eliminated. The soft switching technique provides a solution for these problems.

Fig. 1. Proposed zero voltage transition interleaved buck converter topology.

In this paper, a zero voltage transition technique is proposed for use in a series capacitor buck converter without increasing the component voltage or current stress on the main power switches or diodes. In addition, zero voltage switching (ZVS) of the power switches can be achieved in the whole operating range, and the reverse recovery losses of the output diodes can be reduced due to the limited rate of the turned-off di/dt slew rate. Moreover, the zero current switching (ZCS) and zero current turn-on for the auxiliary switch can be achieved to reduce the switching losses of the auxiliary switch. In Fig. 1, the auxiliary circuit is composed of a series connection of the switch S_a1, the diode D_a1 and the inductor L_a1, and a series connection of the switch S_a2, the diode D_a2 and inductor L_a2, which are also paralleled with the output inductors L₁ and L₂, respectively. The auxiliary switches S_a1 and S_a2 are turned-on before the arrival of the gate pulse of the main switches S₁ and S₂ and they provide negative current through the switches S₁ and S₂. Zero voltage switching for the switches S₁ and S₂ can be achieved.

B. Operation Principle

In order to simplify the analysis of the proposed converter, the following assumptions are made. 1) All of the semiconductor devices in the proposed converter, which include the power switch S₁ and S₂, and the auxiliary switches S_a1 and S_a2, are ideal except for the anti-parallel diodes and output capacitors. The output diodes D₁ and D₂, and the auxiliary diodes D_a1 and D_a2 are ideal except for the stray capacitors. 2) The output capacitor C_o and the series capacitor C₁ are very large so that the voltages V_o and V_C1 can be considered as constants in a switching cycle. 3) The auxiliary switches S_a1 and S_a2 are turned-on before the main power switches S₁ and S₂, respectively. 4) The converter is operated in the steady state.

Fig. 2 shows key waveforms of the proposed converter, where v_gs is the gate pulse of the power switches S₁,S₂,S_a1,S_a2, and the gate pulse of the switches S₂ and S_a2 have a 180⁰ shift delay to the switches S₁ and S_a1, respectively. In addition, the auxiliary switches S_a1 and S_a2 are turned-on before the main power switches S₁ and S₂. i_La1 and i_La2 are the currents through the auxiliary inductors L_a1 and L_a2; i_s1 and i_s2 are the currents through the switches S₁ and S₂; and i_D1 and i_D2 are the currents through the output diodes D₁ and D₂. In the proposed converter, there exist ten operation modes in a switching cycle, and the equivalent circuits of proposed converter for each operation mode are shown in Fig. 3.

Fig. 2. Key waveforms of the proposed converter.

Fig. 3. Operational modes of the proposed converter.

Mode 1 [t₀～t₁]: At t=t₀, the gate pulse for the power switch S_a1 is turned to on, the auxiliary switch S_a1 is turned-on, and the switches S₁, S₂ and S_a2 are turned-off. The output inductor current is freewheeling through the output diodes D₁ and D₂. Because of the turned-on auxiliary switch S_a1, the voltage across the auxiliary inductor is equal to the output voltage. In addition, the current i_La1 is linearly increased and current i_D1 is linearly decreased. When the current i_D1 is decayed to zero, the diode D₁ is turned-off and this mode is ended. In this interval, the current i_La1 can be expressed as:

\(i_{\mathrm{La}1}(t)=\frac{V_{\mathrm{o}}}{L_{a 1}}\left(t-t_{0}\right)\)       (1)

At the end of this interval, the current i_La1 is equal to I_o/2－Δi_L1/2, since the diode D₁ is decayed to zero, where I_o is output current, V_o is the output voltage, and Δi_L1 is the peak-peak current ripple of the inductor L₁. Thus, the interval time can be obtained as:

\(\Delta T_{10}=\frac{I_{0} / 2-\Delta i_{L 1} / 2}{V_{0} / L_{a 1}}\)       (2)

Mode 2 [t₁～t₂]: At t=t₁, the current i_D1 is decayed to zero and the diode D₁ is turned-off. In this mode, due to the continued turn-on of the switch S_a1, the stray capacitor of the switch S₁ and the diode D₁ are resonant with the auxiliary inductor L_a1. In addition, the equivalent resonant capacitor is equal to the parallel stray capacitor of the switches S₁ and S₂ and the diode D₁. After half of a resonant period, the current i_La1 is returned to I_o/2－Δi_L1/2, and equal to the current i_L1. At the end this interval, the voltage across the diode D₁ rises up to the difference of the input voltage and the capacitor voltage V_C1. In addition, the voltage across the switch S₁ is decayed to zero. Then the gate pulse of the switch S₁ is arrives. In addition, the zero voltage switching of the power switch S₁ can be achieved and the switching losses can be eliminated. Based on the analysis, the circuit equation can be obtained as:

\(\left\{\begin{array}{l} -C_{e q} \frac{\mathrm{d} v_{S 1}(t)}{\mathrm{d} t}=i_{L a 1}(t)-\left(I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2\right) \\ L_{a 1} \frac{\mathrm{d} i_{\mathrm{La}1}(t)}{\mathrm{d} t}=V_{\mathrm{o}}-V_{\mathrm{in}}+V_{C 1}+v_{\mathrm{s} 1}(t) \end{array}\right.\)       (3)

i_La1 and v_S1 can be solved according to equation (3) with the initial condition i_La1(t₀)= I_o/2－Δi_L1/2, v_S1(t₀)=V_in－V_C1. Therefore, the auxiliary inductor current and drain-source across the switch S₁ can be expressed as:

\(\left\{\begin{array}{l} i_{\mathrm{La}1}(t)=\left(I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2\right)+\left(V_{\mathrm{o}} / Z_{\mathrm{r} 1}\right) \cdot \sin \left(\omega_{\mathrm{r} 1} t\right) \\ v_{s 1}(t)=V_{\mathrm{in}}-V_{C 1}+\left(\cos \left(\omega_{\mathrm{r}1} t\right)-1\right) \cdot V_{\mathrm{o}} \end{array}\right.\)       (4)

Where the character impedance \(Z_{\mathrm{r}1}=\sqrt{L_{a 1} / C_{\mathrm{eq}}}\) and the resonant angular frequency \(\omega_{\mathrm{r}1}=1 / \sqrt{L_{\mathrm{a}1} C_{\mathrm{eq}}}\). In addition, C_eq1=C_S1+C_S2+C_d1 and C_s1, C_S2,C_d1 are the stray capacitors of the power switches S1 and S2 and the diode D₁.

The time of this interval is:

\(\Delta T_{21}=\pi \sqrt{L_{\mathrm{a}1} C_{\mathrm{eq} 1}}\)       (5)

Mode 3 [t₂～t₃]: At t=t₂, the gate pulse of the switch S₁ is achieved since the voltage across the switch S₁ was decayed to zero and anti-parallel diode of the switch S₁ was conducted in the previous mode. The auxiliary switch S_a1 continues conducting and voltage across the inductor L_a1 is equal to the difference of the input voltage V_C1 and the output voltage V_o. Thus, the current i_La1 is linearly decreased. In addition, the inductor current i_L1 is increased at the rate of (V_in－V_C1－V_o)/L₁, and the current i_L2 is freewheeling with the diode D2. In this interval, the following equations can be obtained as:

\(i_{\mathrm{La}1}(t)=\left(I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2\right)-\frac{V_{\mathrm{in}}-V_{C 1}-V_{\mathrm{o}}}{L_{\mathrm{a}1}}\left(t-t_{2}\right)\)       (6)

\(i_{\mathrm{L}1}(t)=i_{\mathrm{L} 1}\left(t_{2}\right)+\frac{V_{\mathrm{in}}-V_{C 1}-V_{\mathrm{o}}}{L_{1}}\left(t-t_{2}\right)\)       (7)

When the current i_La1 is decreased to zero, the current through the switch S₁ is equal to the inductor current i_L1, and this mode ends. Thus, the time interval is:

\(\Delta T_{32}=\frac{I_{o} / 2-\Delta i_{L 1} / 2}{\left(V_{\text {in }}-V_{C 1}-V_{0}\right) / L_{a 1}}\)       (8)

Mode 4 [t₃～t₄]: At t=t₃, the current through the switch S_a1 is decayed to zero, and zero current turn-off for the auxiliary switch S_a1 can be achieved. The current i_S1 is equal to the current i_L1 through inductor L₁, and the current i_L1 is still linearly increased with the rate of (V_in－V_C1－V_o)/L₁. The diode D₂ is provided as the following path for the inductor current i_L2.

Mode 5 [t₄～t₅]: At t=t₄, the gate pulse of the switch S₁ disappears and the switch S₁ is turned-off. Then, the currents i_L1 and i_L2 freewheel through the diodes D₁ and D₂, and the currents i_L1 and i_L2 are decreased with the rates of V_o/L₁ and V_o/L₂.

Mode 6 [t₅～t₆]: After half of a switching period, the gate pulse of the auxiliary switch S_a2 is arrived at and the auxiliary switch S_a2 is turned-on. The auxiliary current i_La2 is increased linearly with the rate of V_o/L_a2. The currents i_L1 and i_L2 are freewheeling through the diodes D₁ and D₂. In this interval, the current i_La2 can be expressed as:

\(i_{\mathrm{La} 2}(t)=\frac{V_{\mathrm{o}}}{L_{a 2}}\left(t-t_{5}\right)\)       (9)

When the current i_La2 is increased and becomes equal to the current i_L2, zero current turn-off for the diode D₂ is realized. At the end of this mode, the current i_La2 is equal to I_o/2－Δi_L2/2, where Δi_L2 is the current ripple of the inductor L₂. Thus, the interval time can be obtained as:

\(\Delta T_{65}=\frac{I_{o} / 2-\Delta i_{\mathrm{L} 2} / 2}{V_{\mathrm{o}} / L_{\mathrm{a} 2}}\)       (10)

Mode 7 [t₆～t₇]: At t₆, the diode D₁ is turned-off at zero current. The auxiliary switch S_a2 is continuously turned-on, the stray capacitor of the switch S₂ and the diode D₂ is resonant with the auxiliary inductor L_a2, and the equivalent resonant capacitor is equal to the parallel of C_s2 and C_d2. After half of a resonant period, the current i_La2 returns to I_o/2－Δi_L1/2, and is equal to the current i_L2. At this end of this interval, the voltage across the diode D₂ is equal to V_C1, and the drain-source voltage across the switch S₂ is equal to zero. Thus, the condition for the zero voltage switching of the switch S₂ is guaranteed. Based on the analysis, the circuit equation can be obtained as:

\(\left\{\begin{array}{l} -C_{e q} \frac{\mathrm{d} v_{S 2}(t)}{\mathrm{d} t}=i_{L a 2}(t)-\left(I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2\right) \\ L_{a 2} \frac{\mathrm{d} i_{\mathrm{La}}(t)}{\mathrm{d} t}=V_{\mathrm{o}}-V_{C 1}+v_{s 2}(t) \end{array}\right.\)       (11)

i_La1 and v_S1 can be solved according to equation (11) with the initial conditions i_La2(t₀)= I_o/2－Δi_L1/2 and v_S2(t₀)= V_C1. Therefore, the auxiliary inductor current and drain-source across the switch S₁ can be expressed as:

\(\left\{\begin{array}{l} i_{\mathrm{La} 2}(t)=\left(I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2\right)+\left(V_{\mathrm{o}} / Z_{\mathrm{r} 2}\right) \cdot \sin \left(\omega_{\mathrm{r} 2} t\right) \\ v_{s 2}(t)=V_{C 1}+\left(\cos \left(\omega_{\mathrm{r} 2} t\right)-1\right) \cdot V_{\mathrm{o}} \end{array}\right.\)       (12)

Where the character impedance \(Z_{\mathrm{r} 2}=\sqrt{L_{a 2} / C_{\mathrm{eq} 2}}\), the resonant angular frequency \(\omega_{\mathrm{r} 2}=1 / \sqrt{L_{\mathrm{a} 2} C_{\mathrm{eq} 2}}\) and C_eq2= C_S2+C_d2. In addition, C_S2 and C_d2 are the stray capacitors of the power switch S₂ and the diode D₂, respectively.

The time of this interval is:

\(\Delta T_{76}=\pi \sqrt{L_{\mathrm{a} 2} C_{\mathrm{eq} 2}}\)       (13)

Mode 8 [t₇～t₈]: At t=t₇, the gate pulse of the switch S₂ is achieved. The difference of the currents i_La2 and i_L2 is following through the switch S₂, and the anti-parallel diode for the switch S₂ is conducted. Thus, the zero voltage switching of the switch S₂ is guaranteed. The current through the auxiliary inductor and the auxiliary switch S_a2 is decreased at the rate of (V_o－V_C1)/L_a2, and the current i_S2 is increased. When the current i_La2 is decayed to zero, the current i_S2 is equal to the current i_L2, the zero current switching for the auxiliary switch is achieved and this mode ends. Moreover, the diode D₁ provides the following path for the output inductor L₁. In this interval, the following equations can be obtained as:

\(i_{\mathrm{La} 2}(t)=\left(I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2\right)-\frac{V_{C 1}-V_{\mathrm{o}}}{L_{\mathrm{a} 2}}\left(t-t_{7}\right)\)       (14)

\(i_{\mathrm{L} 2}(t)=i_{\mathrm{L} 2}\left(t_{7}\right)+\frac{V_{C 1}-V_{\mathrm{o}}}{L_{2}}\left(t-t_{7}\right)\)       (15)

When the current i_La2 is decreased to zero, this mode ends. Thus, the time interval is:

\(\Delta T_{87}=\frac{I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2}{\left(V_{C 1}-V_{\mathrm{o}}\right) / L_{a 2}}\)       (16)

Mode 9 [t₈～t₉]: At t=t₈, the current i_La2 is decreased to zero, and the auxiliary switch S_a2 is turned-off at zero current. The capacitor C₁ provides the energy transfer to the load-side, and the diode D₁ provides the following path for the inductors L₁ and L₂. The current i_L1 is decreased with the rate of V_o/L₁, and the current i_L2 is increased with the rate of (V_C1－V_o)/L₂. Thus, the interleaved current is flowing through the diode D₁, and the current ripple of i_D1 can be reduced. The following equation can be obtained as:

\(i_{\mathrm{L} 1}(t)=i_{\mathrm{L} 1}\left(t_{8}\right)-\frac{V_{\mathrm{o}}}{L_{1}}\left(t-t_{8}\right)\)       (17)

\(i_{\mathrm{L} 2}(t)=i_{\mathrm{L} 2}\left(t_{8}\right)+\frac{V_{C 1}-V_{\mathrm{o}}}{L_{2}}\left(t-t_{8}\right)\)       (18)

\(i_{\mathrm{D}1}(t)=i_{\mathrm{L} 1}(t)+i_{\mathrm{L} 2}(t)\)       (19)

Mode 10 [t₉～t₁₀]: At t=t₉, the gate pulse for the power switch S₂ disappears and the switch S₂ is turned-off. The diodes D₁ and D₂ provide the following path for the inductors L₁ and L₂, respectively. The currents i_L1 and i_L2 are decreased linearly with the rates of V_o/L₁ and V_o/L₂. When the gate pulse for the auxiliary switch S_a1 is achieved, the next switching begins again.

III. PERFORMANCE ANALYSIS OF THE PROPOSED CONVERTER

A. Voltage Transfer Gain

Based on the above analysis, in the case of D<0.5, the principle of the voltage-second balance is applied to the output inductors L₁ and L₂, and the following equations can be obtained as:

\(\left(V_{\text {in }}-V_{C 1}-V_{\mathrm{o}}\right) D T_{\mathrm{s}}=V_{\mathrm{o}}(1-D) T_{\mathrm{s}}\)       (20)

\(\left(V_{\mathrm{C}1}-V_{\mathrm{o}}\right) D T_{\mathrm{s}}=V_{\mathrm{o}}(1-D) T_{\mathrm{s}}\)       (21)

The voltage across the series capacitor and the DC voltage ratio can be expressed as:

\(V_{\mathrm{C}1}=\frac{1}{2} V_{\mathrm{in}} \quad M=\frac{V_{\mathrm{in}}}{V_{\mathrm{o}}}=\frac{1}{2} D\)       (22)

It can be seen from equation (22) that the additional auxiliary zero voltage transition circuit has no effect on the voltage transfer gain. Moreover, the DC voltage ratio of the proposed converter is half that of the traditional interleaved buck converter. Thus, a higher step down ratio can be achieved when compared with the traditional buck converter.

B. Soft Switching Condition

1) Condition of Zero Voltage Switching for the Power Switches S₁ and S₂: Based on the analysis in section II, in order to achieve zero voltage switching of the power switches S₁ and S₂, there needs to be sufficient time to build the auxiliary inductor current and to decrease the voltage across the switch to zero. Therefore, the currents i_La1 and i_La2 should be made greater than the minimum of the currents i_L1 and i_L2. In addition, they should complete the energy commutation of component in the converter. Thus, the requirement of the time interval of the auxiliary circuit for the switches S₁ and S₂ can be obtained as:

\(D_{\mathrm{a}} T_{\mathrm{s}}>\Delta T_{10}+\Delta T_{21}=\frac{I_{0} / 2-\Delta i_{L 1} / 2}{V_{\mathrm{o}} / L_{a 1}}+\pi \sqrt{L_{\mathrm{a}1} C_{\mathrm{eq} 1}}\)       (23)

\(D_{\mathrm{a}} T_{\mathrm{s}}>\Delta T_{65}+\Delta T_{76}=\frac{I_{\mathrm{o}} / 2-\Delta i_{\mathrm{L} 2} / 2}{V_{\mathrm{o}} / L_{\mathrm{a} 2}}+\pi \sqrt{L_{\mathrm{a} 2} C_{\mathrm{eq} 2}}\)       (24)

Where D_a is the duty cycle of the auxiliary switches S_a1 and S_a2. T_s is the switching period. The current ripple of the output inductor currents i_L1 and i_L2 can be expressed as:

\(\Delta i_{\mathrm{L} 1}=\frac{V_{\mathrm{o}}}{L_{1}}(1-D) T_{\mathrm{s}}, \quad \Delta i_{\mathrm{L} 2}=\frac{V_{\mathrm{o}}}{L_{2}}(1-D) T_{\mathrm{s}}\)       (25)

2) Condition of Zero Current Switching for the Power Switches S_a1 and S_a2: In order to achieve zero current switching for the auxiliary switches S_a1 and S_a2, the current through the switches S_a1 and S_a2 should be reduced to zero. Thus, after the main switches S₁ and S₂ are turned-on, it needs external time to decay the currents i_La1 and i_La2 to zero. The condition of the ZCS switching for the auxiliary switches S_a1 and S_a2 can be obtained as:

For switch S_a1:

\(\begin{array}{l} D_{\mathrm{a}} T_{\mathrm{s}}>\Delta T_{10}+\Delta T_{21}+\Delta T_{32} \\ =\frac{I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2}{V_{\mathrm{o}} / L_{a 1}}+\pi \sqrt{L_{\mathrm{a}1} C_{\mathrm{eq} 1}}+\frac{I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2}{\left(V_{\mathrm{in}}-V_{C 1}-V_{\mathrm{o}}\right) / L_{a 1}} \end{array}\)       (26)

For switch S_a2:

\(\begin{array}{l} D_{\mathrm{a}} T_{\mathrm{s}}>\Delta T_{65}+\Delta T_{76}+\Delta T_{87} \\ =\frac{I_{\mathrm{o}} / 2-\Delta i_{\mathrm{L} 2} / 2}{V_{\mathrm{o}} / L_{\mathrm{a} 2}}+\pi \sqrt{L_{\mathrm{a} 2} C_{\mathrm{eq} 2}}+\frac{I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2}{\left(V_{C 1}-V_{\mathrm{o}}\right) / L_{a 2}} \end{array}\)       (27)

Therefore, only the minimum times of the auxiliary switches S_a1 and S_a2 are greater than equations (26) and (27), and the ZCS switching can be achieved.

3) Zero Current Turn-off for the Output Diodes D₁ and D₂: Due to the existence of ZVT of the auxiliary circuit in mode 1, the turn-off slew rate of the current through the diodes D₁ and D₂ is limited by the auxiliary inductors L_a1 and L_a2. Thus, soft turn-off for the output diodes D₁ and D₂ can be achieved and the reverse recovery losses of the fast-recovery diodes D₁ and D₂ are reduced.

C. Selection of the Resonant Inductors L_a1 and L_a2

The resonant inductors L_a1 and L_a2 control the turn-off di/dt slew rate of the output diodes D₁ and D₂, and the reverse-recovery-related switching losses for the diodes can be reduced by slowing the turn-off di/dt slew rate. Thus, the resonant inductor is larger, and the reverse-recovery-related switching losses are lower. However, with a larger value of the inductors L_a1 and L_a2, the resetting time of the resonant inductor becomes longer, and the conduction losses for the auxiliary switches are increased. Therefore, there exists a trade-off between the reverse-recovery-related switching losses for the diodes and the conduction losses for the auxiliary switches. Generally, the turn-off slew rate for the output diodes is keeping below 100A/µs to nearly eliminate the reverse-recovery-related switching losses of the fast recovery diodes, and the resetting time of the auxiliary inductor is within four times the diode’s specified reverse recovery time t_rr. Thus, the selection condition of the resonant inductors L_a1 and L_a2 can be obtained as:

\(\left\{\begin{array}{l} V_{\mathrm{o}} / L_{a 1} \leq 100 \mathrm{A} / \mu \mathrm{s} \\ \frac{I_{\mathrm{o}} / 2-\Delta i_{L 1} / 2}{\left(V_{\mathrm{in}}-V_{\mathrm{C}1}-V_{\mathrm{o}}\right) / L_{a 1}}<4 t_{\mathrm{rr}} \end{array}\right.\)       (28)

\(\left\{\begin{array}{l} V_{\mathrm{o}} / L_{a 2} \leq 100 \mathrm{A} / \mu \mathrm{s} \\ \frac{I_{\mathrm{o}} / 2-\Delta i_{L 2} / 2}{\left(V_{\mathrm{C}1}-V_{\mathrm{o}}\right) / L_{a 2}}<4 t_{\mathrm{rr}} \end{array}\right.\)       (29)

D. Stress Analysis and Selection of the Switches S₁, S₂ and S_a1, S_a2

1) The Main Power Switches S₁ and S₂, and the Diodes D₁ and D₂: Based on the above analysis, the voltage stress of the switch S₁ is equal to half of the input voltage, and the voltage stress of the switch S₂ is equal to the input voltage. The voltage stress of the output diodes D₁ and D₂ are clamped to half of the input voltage. Thus, the voltage stress can be expressed as:

\(V_{\mathrm{S} 1, \text {stress}}=0.5 V_{\mathrm{in}}, V_{\mathrm{S} 2, \text {stress}}=V_{\mathrm{in}} ; \quad V_{\mathrm{D} 1, \text {stress}}=V_{\mathrm{D} 2, \text {stress}}=0.5 V_{\mathrm{in}}\)       (30)

2) The Auxiliary Switches S_a1 and S_a2: It can be seen from mode 4 and mode 9 that when the auxiliary switches S_a1 and S_a2 are turned-off, and the voltage across the auxiliary switch S_a1 series diode D_a1 or the auxiliary switch S_a2 series diode D_a2 is equal to the difference of half of the input voltage and the output voltage. Moreover, the zero current turn-on and zero current switching for the auxiliary switches S_a1 and S_a2 can be achieved. Thus, the switching turn-on losses and turn-off losses are very small and can be neglected. In the proposed converter, the conduction losses of the auxiliary switches should be carefully considered. In order to simplify the analysis, the quasi stepped square wave is assumed, as shown in fig. 4, for the auxiliary current. Thus, the average current stress and RMS current stress of the auxiliary circuit branch can be expressed as:

\(I_{\text {ave }}=\frac{1}{T_{\mathrm{s}}}\left(\left(\Delta T_{1}+\Delta T_{3}\right) \cdot \frac{1}{2}\left(\frac{I_{o}}{2}-\frac{\Delta i_{L 1,2}}{2}\right)+\left[\left(\frac{I_{o}}{2}-\frac{\Delta i_{L 1,2}}{2}\right)+\frac{2 V_{o}}{\pi Z_{\mathrm{r}}}\right] \cdot \Delta T_{2}\right)\)       (31)

\(\begin{array}{l} I_{\mathrm{rms}}=\sqrt{\frac{1}{T_{\mathrm{s}}} \int i_{L a}^{2} \mathrm{d} t} \\ \left.=\sqrt{\frac{1}{T_{\mathrm{s}}}\left(\Delta T_{1}+\Delta T_{3}\right) \cdot \frac{1}{4}\left(\frac{I_{\mathrm{o}}}{2}-\frac{\Delta i_{L 1,2}}{2}\right)^{2}+\left[\left(\frac{I_{\mathrm{o}}}{2}-\frac{\Delta i_{L1,2}}{2}\right)+\frac{2 V_{\mathrm{o}}}{\pi Z_{\mathrm{r}}}\right]^{2} \cdot \Delta T_{2}}\right) \end{array}\)       (32)

Where the time intervals ΔT₁, ΔT₂ and ΔT₃ are the intervals of the auxiliary current charging time, resonant time and discharging time, respectively. Δi_L1,2 is the peak-peak ripple of the current i_L1 or i_L2. I_o is the output load current.

Fig. 4. Equivalent waveform of the auxiliary inductor current i_La1 or i_La2.

IV. LOSS ANALYSIS

In order to evaluate the performance of the proposed converter, a loss breakdown of the ZVT series capacitor interleaved buck converter should be given. Based on the above analysis, through appropriate selection of the parameters of the proposed converter, the zero voltage switching of the main switches and the zero current switching of the auxiliary switches, the reverse-recovery switching losses of the main diodes can be eliminated over wide load and input voltage ranges. Therefore, when compared with the traditional series capacitor buck converter, the efficiency of the proposed converter has an advantage since the additional conduction losses caused by the auxiliary circuit are less than the reduced switching losses. Thus, the loss factors of the proposed converter considered in the analysis are as follows. 1) The conduction losses and turn-off loss of the main switches S1 and S2. 2) The conduction losses of the main diodes D1 and D2. 3) The conduction losses of the auxiliary switches and diodes.Firstly, the turn-on switching losses and capacitive discharging losses of the power switches are eliminated. Thus, only the conduction losses and turn-off losses of the main switches are considered in the loss analysis. For the switches S1 and S2, the related losses can be expressed as:

\(\begin{aligned} P_{s w\left(S_{\mathrm{i}}\right)}=& \sum_{i} R_{\mathrm{ds}, o n\left(S_{i}\right)} i_{r m s\left(S_{i}\right)}^{2}+\sum_{i} \frac{1}{2} V_{\left(S_{i}\right)} I_{\left(S_{i}\right)} t_{o f f} f_{s} \\ =& R_{\mathrm{ds}, o n\left(S_{1}\right)} i_{r m s\left(S_{1}\right)}^{2}+R_{\mathrm{ds}, o n\left(S_{2}\right)} i_{r m s\left(S_{2}\right)}^{2} \\ &+\frac{1}{2} V_{\left(S_{1}\right)} I_{\left(S_{1}\right)} t_{o f f} f_{s}+\frac{1}{2} V_{\left(S_{2}\right)} I_{\left(S_{2}\right)} t_{o f f} f_{s} \end{aligned}\)       (33)

Next, due to the limited turned-off rate of the output diodes, the reverse-recovery switching losses are neglected in the proposed converter. Thus, only the conduction losses are considered. For the output diodes D₁ and D₂, the related losses can be obtained as:

\(P_{s w\left(S_{i}\right)}=\sum_{i} V_{F} I_{\left(D_{i}\right)}=V_{F} I_{(D 1)}+V_{F} I_{(D 2)}\)       (34)

Finally, considering the losses caused by the auxiliary circuit, and due to the zero current turn-on and zero current switching turn-off for the auxiliary switches S_a1 and S_a2, the switching related losses can be neglected. Therefore, for the auxiliary circuit, the conduction losses can be expressed as:

\(\begin{array}{l} P_{s w\left(S_{\mathrm{ai}}, D_{a i}\right)}=\sum_{i} R_{\mathrm{ds}, o n\left(S_{a i}\right)} i_{r m s\left(S_{a i}\right)}^{2}+\sum_{i} V_{F} I_{\left(D_{a i}\right)} \\ =R_{\mathrm{ds}, o n\left(S_{a 1}\right)} i_{r m s\left(S_{a 1}\right)}^{2}+R_{\mathrm{ds}, o n\left(S_{a 2}\right)} i_{r m s\left(S_{a 2}\right)}^{2}+V_{F} I_{(D a 1)}+V_{F} I_{(D a 2)} \end{array}\)       (35)

A comparison losses analysis of the proposed converter, the traditional series capacitor buck converter and the traditional interleaved buck converter are shown in Table I. It can be seen from this table that the conduction losses of the switches S₁ and S₂ are the same for the three converters due to half of duty cycles with the same output voltage. Moreover, the switching losses of the main switch and capacitive losses are eliminated in the proposed converter when compare with the series capacitor converter and the interleave buck converter. The reverse recovery switching losses for the output diodes can be eliminated in the proposed converter. However, the conduction losses of the auxiliary circuit are added and zero current switching for auxiliary switch is achieved. Thus, the condition where the additional conduction losses are smaller than the reduced switching losses of the main switch and the reverse recovery switching losses for the output diodes is guaranteed, and the efficiency of the proposed converter can be improved.

TABLE I LOSSES EQUATIONS OF THE PROPOSED CONVERTER OPERATED AT THE STEADY STATE

V. EXPERIMENTAL RESULTS

A. Design Example

In order to verify theoretical analysis of the proposed converter, an experimental prototype of the ZVT series capacitor buck converter was established in the laboratory. The specifications of the converter are given as follows: 1) input voltage V_in=100V; 2) output voltage V_o=10V; 3) switching frequency f_s=100kHz. Thus, the duty cycle of the main switches S₁ and S₂ can be calculated as D=0.24. According to the stress analysis in the above section, the IPB020N10N5 is selected for the main power switch S₁, and the switches S_a1 and S_a2. The IPB110N20N3 is selected as the main power switch S₁, and the output diodes D₁, D₂, D_a1 and D_a2 are MBR40250T (V_F=0.86V,T_rr=35ns,C_T=500pF). Based on the previous analysis, the auxiliary inductor should have a trade-off between additional conduction losses and duty cycle laminations of the auxiliary switch. Therefore, auxiliary inductors L_a1=L_a2=2.2µH are selected in this paper. In order to achieve zero voltage turned-on for the main switches S₁ and S₂, the duty cycle of the auxiliary switch can satisfy equations (24) and (25). Thus, the turn-on time for the auxiliary switch should be larger than 0.4µs. Furthermore, in order to achieve zero current turn-off for the auxiliary switches S_a1 and S_a2, based on the equations (27) and (28), the duty cycle D_a should be larger than 0.48. The selected parameter of the passive components and semiconductors are shown in Table II.

TABLE II PARAMETERS OF THE PROPOSED CONVERTER

B. Waveforms

Fig. 5 shows gate pulse waveforms for the main switch and auxiliary switch. Key waveforms of the proposed converter are given in Fig. 6. It can be seen from Fig. 6 that the voltage stresses of the switch S₁ and the diodes D₁ and D₂ are equal to half of the input voltage V_in. It can also be seen that the voltage of the switch S₂ is a trapezoidal-type waveform. Thus, it corresponds to the theoretical analysis. In addition, the turned-off loss can be reduced, and the switching losses are reduced. Moreover, the voltage across the intermediate capacitor is equal to half of the input voltage. Thus, auto current sharing can be guaranteed. The operating time of the auxiliary circuit is very low and the current through the auxiliary circuit has no effect on the main power switches. Voltage and current waveforms of the main switch in the proposed converter are shown in Fig. 7. It can be seen from the full load and half load waveforms in Fig. 7(a) and (b) and (c) and (d), that the ZVS for the switches S₁ and S₂ is achieved and switching losses are reduced due to the low turn-off di/dt.

Fig. 5. Gate pulse waveforms for the main switch and auxiliary switch. (a) Gate pulse of the switches S₁ and S₂. (b) Gate pulse of the switches S_a1 and S₁.

Fig. 6. Key waveforms of the proposed converter. (a) Voltage across the main switches S₁ & S₂ and the diodes D₁ & D₂. (b) Voltage V_C1 of the intermediate energy storage capacitance and output voltage V_o. (c) Current through the auxiliary inductor L_a1.

Fig. 7. ZVS waveforms of the main switch S₁ and the switch S₂. (a) At full load. (b) At full load. (c) At 50% load. (d) At 50% load.

Fig. 8 shows voltage waveforms of the auxiliary switches S_a1/S_a2 and current waveforms of the auxiliary inductor L_a1/L_a2. It can be seen from Fig. 8 that the zero current and zero voltage of S_a1/S_a2 can be achieved at full load and 50% load. In the experiment results, the auxiliary switch S_a1/S_a2 and diode D_a1/D_a2 share the voltage stress of V_in/2. Thus, the voltage stress across the switches S_a1/S_a2 is about V_in/4. The zero current turn-on and zero voltage turn-on of the switches S_a1/S_a2 is obtained since the current through the auxiliary inductor commutes with the output diode. In addition, when the current through the diode is decreased to zero, the current i_La1/i_La2 increased. Therefore, the added switching losses on the auxiliary switches are very low and can be ignored. Moreover, the additional conduction losses caused by the auxiliary circuit are less than the reduced switching losses due to the low RMS of the auxiliary current. Thus, the performance of the proposed converter can be improved.

Fig. 8. Voltage waveforms of the switch S_a1/S_a2. (a) At full load. (b) At full load. (c) At 50% load. (d) At 50% load.

C. Efficiency

Fig. 9 shows the efficiency measured under different load conditions when the input voltage is 100 V. As can be seen in this figure, the proposed converter has improved efficiency when compared with the traditional series buck converter. It is also indicated that the additional conduction losses of the proposed converter are less than the reduced switching loess of the main switches and reverse recovery loss of the diodes. This occurs in the proposed converter because the ZCS-ZVS PWM circuit cell is utilized, zero voltage transition of the main power switches are achieved and zero current switching of the auxiliary switches are obtained in a wide operating range. Moreover, the additional conduction losses caused by the auxiliary circuit are very small due to the small operating time of the auxiliary circuit. Furthermore, the proposed technique does not increase the voltage stress or current stress of the main switches and diodes, as can be seen in the experimental waveforms. Thus, the proposed converter has better performance when compared with the traditional series capacitor buck converter.

Fig. 9. Efficiency comparison of the proposed converter.

VI. TOPOLOGY VARIATIONS OF THE PROPOSED CONVERTER

In the above analysis, the zero voltage transition series capacitor interleaved buck converter prevails over the traditional series buck converter and the interleaved buck converter. However, two additional auxiliary switches, two diodes, and auxiliary inductors are used to obtain this character. As a result, the cost and complexity of the proposed converter are increased. In order to simplify the proposed converter topology, two topology variations of the proposed converter are shown in Fig. 10. In the ZVT auxiliary circuit for the proposed converter, the branch of the auxiliary series diode and inductor is commonly used, and the derived topology is shown in Fig. 10(a). In this figure, the gate pulse waveforms of the main switch and the auxiliary switch are the same as the previously analyzed converter in this paper. Thus, one auxiliary inductor and diode are eliminated.

Fig. 10. Topology variations of the proposed converter.

In Fig. 10(b), only one auxiliary switch is utilized. Thus, the gate pulse waveform for the switch S_a should be conducted twice in one switching period.

VII. CONCLUSION

This paper presented a zero voltage transition (ZVT) series capacitor interleaved buck converter. The operational principle and a relevant analysis of the proposed converter are developed. In addition, the DC voltage gain ratio, the soft switching condition and a design guideline of the critical parameters are given in this paper. Furthermore, a loss analysis of the proposed converter is described. Experimental results show that zero voltage transition of the main power switches are achieved and that the reverse recovery losses of the output diodes are reduced without increasing the voltage stress or current stress of the main switches and diodes. The additional conduction losses caused by the auxiliary circuit are very small due to the small operating time of the auxiliary circuit. Based on these merits, the proposed zero voltage transition (ZVT) series capacitor interleaved buck converter with high step-down power-conversion can be used in the power sources for microprocessors, automotive applications, LED drivers, solar-power regulators and so on.