Fig. 1. Concept of proposed PA.
Fig. 2. Overall architecture.
Fig. 3. Simulated fundamental and second order harmonic power versus RF input power.
Fig. 4. Simulated operation of power detector.
Fig. 5. Simulated power detector output DC voltage versus RF input power.
Fig. 6. Full-schematic of the proposed linear PA using pre-distortion method.
Fig. 7. Simulated capacitance and quality factor of variable capacitors.
Fig. 8. Simulated Smith-chart of input node at PA.
Fig. 9. Simulated total gate width of MOS capacitor versus output power of PA.
Fig. 10. Simulated gain versus output power of PA.
Fig. 11. Simulated PAE versus output power of PA.
Fig. 12. Simulated DC power consumption of power detector.
Fig. 13. Simulated output power versus input power.
Table 1. Summary of linear power amplifier performance.
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