그림 1. 1세대 SuperFlash 셀의 공정단면도. Fig. 1. Process cross-section of a 1st generation SuperFlash cell.
그림 2. Row 구동회로. Fig. 2. Row driver circuit.
그림 3. Write 모드시 BL 구동회로 (a) WBL 스위치 회로 (b) PBL 스위치 선택회로. Fig. 3. BL drive circuit in write mode: (a) WBL switching circuit and (b) PBL switch select circuit.
그림 4. Read BL 스위치 회로. Fig. 4. Read BL switch circuit.
그림 5. 설계된 current S/A 회로[6]. Fig. 5. The designed current S/A circuit[6].
그림 6. 기존의 VPP 단위 전하펌프 회로 (a) cross-coupled NMOS 프리차징 방식[17]. (b) boosted gate 전압을 이용한 NMOS 프리차징 방식[18]. Fig. 6. The conventional VPP unit charge pump circuit: (a) cross-coupled NMOS precharging method[17] and (b) NMOS precharging method using boosted gate voltage[18].
그림 7. 새롭게 제안된 VPP 단위 전하펌프 회로. Fig. 7. Newly proposed VPP unit charge pump circuit.
그림 8. 설계된 512Kb eFlash 메모리 IP의 레이아웃 이미지. Fig. 8. Layout image of the designed 512Kb eFlash memory IP.
그림 9. 셀 어레이 관련 선택된 신호와 선택되지 않은 신호의 출력파형 (a) 프로그램 모드 (b) 지우기 모드. Fig. 9. Output waveforms of selected and unselected signals related to the cell array: (a) program mode and (b) erase mode.
표 1. 설계된 512Kb eFlash IP의 주요 특징. Table 1. Major specifications of the designed 512Kb eFlash IP.
표 2. 동작모드에 따른 HV 스위칭 파워의 출력전압. Table 2. Output Voltage of HV switching powers according to operating modes.
표 3. VPP 단위 전하펌프 회로에 따른 펌핑 전류 모의실험 결과. Table 3. Simulation results of pumping currents according to VPP unit charge pump circuit.
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