Interleaved High Step-Up Boost Converter

Abstract

Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

I. INTRODUCTION

Traditional fossil fuel resources are being rapidly depleted, and their continued use will further aggravate environmental degradation. The development of clean energy systems is crucial. Photovoltaic power generation, wind power generation and fuel cell power generation are important clean energy technologies. Systems using photovoltaic cells and batteries to provide clean power have become increasingly common. Therefore, in order to transfer the energy from traditional photovoltaic cells (12-48V) to a traditional 110V/220V AC power grid, it is necessary to use a DC-DC converter to improve the voltage. To achieve a high voltage gain, a cascaded boost converter had been presented in [1]-[4]. Although a large conversion ratio can be achieved, the voltage stress on the active switch is equivalent to the value of a high output voltage. Some converters employ the switched-capacitor technique to a conventional boost converter for a high conversion ratio [5]-[8]. Although the voltage stress of the power switch is reduced when the gain is increased, the efficiency of the converter is reduced since more power switch devices are used. In addition, the use of multiple switched capacitor modules brings a great deal of impulse current, which greatly reduces the stability of the converter. Switched-inductor technology has been combined with basic boost converters to obtain a high voltage [9]-[11], and the reverse recovery of the output diode is effectively suppressed. However, there are larger ripples on both the high input current and the output voltage, which is harmful to photovoltaic cells and the load.

Considering the low ripple of the interleaved structures for high power applications, several interleaved Boost converters were proposed in [12]-[15]. However, the voltage gain was not high enough to be suitable for low voltage renewing energy generated systems. In [16], [17], transformer technology is used to improve the voltage gain. However, this increases the volume of the converter, and reduces both the power density and efficiency. Coupled-inductors were used in [18]-[21]. However, this resulted in hysteresis loss and eddies current loss, which reduce the efficiency of the converter. In addition, the leakage inductance can easily cause voltage spikes across the switches, and voltage clamping techniques are required to limit the voltage stresses on the switches. Consequently, this increases both the design cost and the control difficulty.

In this paper, a new interleaved boost converter is proposed to achieve a high gain and a high efficiency. The topology of proposed converter is shown in Fig. 1. The converter has the following characteristics. (a) It has a higher step-up ratio with same duty cycles. (b) The voltage stresses of the main switches are very low. (c) It is beneficial for reducing the input current ripple and output voltage ripple. (d) The voltage of output capacitance can be automatically shared without an extra control strategy.

Fig. 1. Topology of the proposed converter.

II. OPERATING PRINCIPLES OF THE PROPOSED CONVERTER

To simplify the circuit analysis, the following assumptions are made.

(a) All of the power semiconductors and energy storage components are ideal, which means the on-state resistance of power semiconductors, the forward voltage drop of the diodes, and the equivalent series resistance (ESR) of the inductors and capacitors are ignored.

(b) All of the capacitances are large enough that each of the capacitor voltages can be treated as constant.

(c) The relationship between d₁ and d₂ can be written as d₁=d₂=d, where d₁ and d₂ are the duty cycles of S₁ and S₂, respectively.

(d) The phase difference between the gate driving signals of S₁ and S₂ is 180°.

In the circuit analysis, it is assumed that the converter operates in the continuous conduction mode (CCM) and that the duty ratio of the switches is greater than 0.5. Fig. 2 illustrates operational waveforms of the proposed converter in the CCM during one switching cycle. According to Fig. 2, four operation modes exist in each switching cycle of the proposed converter. Fig. 3 shows an equivalent circuit of the converter in different modes.

Fig. 2. Key waveforms of one cycle during CCM operation.

Fig. 3. Equivalent circuit of each mode in the CCM mode. (a) Mode I and III. (b) Mode II. (c) Mode IV.

Mode I and Mode III: In this mode, the switches S₁ and S₂ are switched on. The diodes D₁, D₂, D₃ and D₄ are off. The current flow path is shown in Fig. 3 (a). At this time, the inductances L₁ and L₂ are charged by the power, and the currents of the inductances L₁ and L₂ are gradually increased. The capacitances C₃ and C₄ in series are combined to supply the load R. When the switch S₂ is off, the converter operates in the next mode.

Mode II: In this mode, the switch S₁ is still in the open state, and the switch S₂ is closed. The diodes D₁ and D₃ are on, and D₂ and D₄ are off. The current flow path is shown in Fig. 3 (b). At this point, the inductance of L₁ is still being charged, and the current of L₁ continues to increase. The capacitor C₁ is charged by the input power. The input power, the inductor L₂ and the capacitor C₂ are connected in series to provide energy to the capacitor C₄ and the load R. The capacitor C₃ releases energy to load R at the same time, and the inductor current i_L2 on L₂ is decreased. When the switch S₂ is switched, the converter operates in mode III. Then the converter operates in mode IV after the switch S₁ is closed.

Mode IV: In this mode, the switch S₁ is still closed, and the switch S₂ is still opened. The diodes D₁ and D₃ are turned off, and the diodes D₂ and D₄ are turned on. The current flow path is shown in Fig. 3 (c). At this point, the inductance of L₁ is still being charged, and the current of L₁ continues to increase. The capacitance C₂ is charged by the input power. The input power, the inductance L₁ and the capacitance C₁ are combined to supply energy to the capacitance C₄ and the load R. The capacitance C₄ also releases energy to the load R, and the inductor current i_L1 on L₁ continue to decrease. The inductance L₂ is still charged and the current on L₂ continues to increase. When the switch tube S₁ is opened, the converter operates in mode I again.

III. STEADY-STATE PERFORMANCE OF THE PROPOSED CONVERTER

A. Voltage Gain and Device Stress in the CCM Mode

The charge is transferred progressively from the input to the output by charging the voltage multiplier stage capacitors. For a converter with three modes (Fig. 3), the voltage gain can be obtained by applying the volt-second equilibrium principle of the boost inductor in a complete working week.

When the switch S₁ is opened, for the inductance L₁:

\(V_{L 1}^{I} * T_{1 o n}=V_{L 1}^{I I} * T_{1 o f f}\)       (1)

Where T_1on is the opening time in one cycle S₁, and T_1off is the turn off time in one cycle.

From Mode I to Mode III, it can be seen that:

\(V_{L 1}^{I}=V_{i n}\)       (2)

By (1) and (2), it can be found that:

\(V_{L 1}^{I I}=\frac{T_{1 o n}}{T_{1 o f f}} V_{L 1}^{I}=\frac{d_{1}}{1-d_{1}} V_{L 1}^{I}=\frac{d_{1}}{1-d_{1}} V_{i n}\)       (3)

Where d₁ is the switching duty cycle for S₁.

When the switch S₂ is opened, for the inductance L₂:

\(V_{L 2}^{I} * T_{2 o n}=V_{L 2}^{I I} * T_{2 o f f}\)       (4)

Where T_2on is the opening time in one cycle for S₂, and T_2off is the turn off time in one cycle.

From Modes I, III and IV, it can be seen that:

\(V_{L 2}^{I}=V_{i n}\)       (5)

By (4) and (5), it can be found that:

\(V_{L 2}^{I I}=\frac{T_{2 o n}}{T_{2 o f f}} V_{L 2}^{I}=\frac{d_{2}}{1-d_{2}} V_{L 2}^{I}=\frac{d_{2}}{1-d_{2}} V_{i n}\)       (6)

Where d₂ is the switching duty cycle for S₂.

By Mode II, it can be seen that the voltage on C₁ is:

\(V_{C 1}=V_{i n}+V_{L 2}^{I I}=V_{i n}+\frac{d_{2}}{1-d_{2}} V_{i n}=\frac{1}{1-d_{2}} V_{i n}\)       (7)

Similarly, the expression of the voltage on the capacitor C₂ can be obtained by Mode IV as:

\(V_{C 2}=V_{i n}+V_{L 1}^{I I}=V_{i n}-\frac{d_{1}}{1-d_{1}} V_{i n}=\frac{1}{1-d_{1}} V_{i n}\)       (8)

By mode IV, the expression of the voltage on the capacitor C₃ can be obtained as:

\(V_{C 3}=V_{i n}+V_{L 1}^{I I}+V_{C 1}=V_{i n}+\frac{d_{1}}{1-d_{1}} V_{i n}+\frac{1}{1-d_{2}} V_{i n}\)       (9)

In the same way, the expression of the voltage on the capacitor C₄ can be obtained by mode II as:

\(V_{C 4}=V_{i n}+V_{L 2}^{I I}+V_{C 2}=V_{i n}+\frac{d_{2}}{1-d_{2}} V_{i n}+\frac{1}{1-d_{1}} V_{i n}\)       (10)

Order d₁=d₂=d:

\(V_{C 3}=V_{C 4}=\frac{2}{1-d} V_{i n}\)       (11)

According to mode I and mode III, it can be found that the expression of the output voltage is as follows:

\(V_{O}=V_{C 3}+V_{C 4}\)       (12)

Take formula (11) into the front of the formula:

\(V_{O}=\frac{4}{1-d} V_{i n}\)       (13)

Therefore, when the proposed converter operates in the current continuous mode of inductance, the voltage gain is:

\(M_{C C M}=\frac{V_{O}}{V_{i n}}=\frac{4}{1-d}\)       (14)

Fig. 4 shows the voltage gain of the proposed converter in the CCM compared with the converters proposed in [16] (n=1) and in [12] under different duty cycles.

Fig. 4. Voltage gain comparison.

During CCM operation, the voltage stresses across S₁, S₂ and D₁~D₄ are written as:

\(V_{S 1}=V_{S 2}=V_{C 1}=V_{C 2}=\frac{V_{O}}{4}\)       (15)

\(V_{D 1}=V_{D 2}=V_{D 3}=V_{D 4}=V_{C 3}=V_{C 4}=\frac{V_{O}}{2}\)       (16)

Fig. 5 shows a comparison of the normalized voltage stresses of the power components with the converter in [16]. It is concluded that the voltage stress values of the power devices are always lower than the high output voltage. Thus, highperformance power devices, including diodes and switches, can be employed to increase efficiency.

Fig. 5. Normalized voltage stresses of the power components.

According to the working principle, the current ripples of the inductor can be derived as:

\(\Delta I_{L m}=\frac{V_{i n} d T_{S}}{L_{m}}\)       (17)

The average currents of I_C1, I_C2, I_C3 and I_CO are zero in the steady-state. Thus, the average currents of the diodes D₁ and D₃ (I_D1 and I_D2) are equal to I_L2,avg/2; and the average currents of the diodes D₂ and D₄ (I_D3 and I_D4) are equal to I_L1,avg/2. The current stresses on S and D₁~D₄ are expressed as:

\(I_{D 1(p e a k)}=I_{D 3(p e a k)}=\frac{\Delta I_{L m}}{2}+\frac{I_{L 2, a v g}}{2}\)       (18)

\(I_{D 2(p e a k)}=I_{D 4(p e a k)}=\frac{\Delta I_{L m}}{2}+\frac{I_{L 1, a v g}}{2}\)       (19)

B. Analysis of the Input Current Ripple under the CCM

As shown in Fig. 6(a), at time t₁, the inductance current and the input current can be expressed as:

\(i_{L_{1}}\left(t_{1}\right)=I_{L 1, a v g}-\frac{(1-d) \Delta i_{L 1}}{2 d}=\frac{2 I_{O}}{1-d}-\frac{V_{i n}(1-d) T_{S}}{2 L_{1}}\)       (20)

\(i_{L 2}\left(t_{1}\right)=I_{L 2, a v g}+\frac{\Delta i_{L 2}}{2}=\frac{2 I_{O}}{1-d}+\frac{V_{i n} d T_{S}}{2 L_{2}}\)       (21)

\(i_{i n}\left(t_{1}\right)=i_{L 1}\left(t_{1}\right)+i_{L 2}\left(t_{1}\right)=\frac{4 I_{O}}{1-d}+\left(\frac{d}{2 L_{2}}-\frac{1-d}{2 L_{1}}\right) V_{i n} T_{S}\)       (22)

Fig. 6. Input current ripple analysis diagrams.

The expression of the input current ripple is obtained as:

\(\Delta i_{i n}=\left|\left(\frac{d}{2 L_{2}}-\frac{1-d}{2 L_{1}}\right)\right| V_{i n} T_{S}\)       (23)

Assuming L₂=nL₁:

\(\Delta i_{i n}=\left|\frac{(n+1) d}{n}-1\right| \frac{V_{i n} T_{S}}{2 L_{1}}\)       (24)

The relationship between the input current ripple and the duty cycle d is given in Fig. 6(b). It can be seen that the inductance value of the converter is designed according to the duty cycle of the converter, and that the zero ripples of the input current can be theoretically realized.

C. Performance Analysis of the Automatic Balance of the Output Voltage of Two Branches

Assuming the duty cycle of the main switch S₁ is d₁, the duty cycle of the main switch S₂ is d₂, and d₁≠d₂. In addition, the MOSFET and power diode usually have some voltage drops which should be considered in practical circuit designs. Assuming V_d to be the voltage drops, by applying the voltage-second balance to the inductance, the discharging voltages of L₁ and L₂ can be obtained as:

\(V_{L 1}^{d i s c}=\frac{d_{1}}{1-d_{1}}\left(V_{i n}-V_{d}\right)\)       (25)

\(V_{L 2}^{d i s c}=\frac{d_{2}}{1-d_{2}}\left(V_{i n}-V_{d}\right)\)       (26)

Two voltage-second equations can be rewritten as:

\(d_{2} T_{S}\left(V_{i n}-V_{d}\right)+\left(1-d_{2}\right) T_{S}\left(V_{i n}-V_{C 1}-2 V_{d}\right)=0\)       (27)

\(d_{1} T_{S}\left(V_{i n}-V_{d}\right)+\left(1-d_{1}\right) T_{S}\left(V_{i n}-V_{C 2}-2 V_{d}\right)=0\)       (28)

The voltages across C₁ and C₂ can be derived as:

\(V_{C 1}=\frac{1}{1-d_{2}} V_{i n}-\frac{2-d_{2}}{1-d_{2}} V_{d}\)       (29)

\(V_{C 2}=\frac{1}{1-d_{1}} V_{i n}-\frac{2-d_{1}}{1-d_{1}} V_{d}\)       (30)

When the main switch S₁ is turned off, the output voltage of branch 1 can be derived as:

\(\begin{aligned} V_{O 1} &=V_{C 3}=V_{i n}+V_{L 1}^{d i s c}+V_{C 1}-2 V_{d} \\ &=\left(\frac{1}{1-d_{1}}+\frac{1}{1-d_{2}}\right) V_{i n}-\left(\frac{1}{1-d_{1}}+\frac{3-2 d_{2}}{1-d_{2}}\right) V_{d} \end{aligned}\)       (31)

Analogously, when the main switch S₂ is turned off, the output voltage of branch 2 can be derived as:

\(\begin{aligned} V_{O 2} &=V_{C 4}=V_{i n}+V_{L 2}^{disc}+V_{C 2}-2 V_{d} \\ &=\left(\frac{1}{1-d_{2}}+\frac{1}{1-d_{1}}\right) V_{i n}-\left(\frac{1}{1-d_{2}}+\frac{3-2 d_{1}}{1-d_{1}}\right) V_{d} \end{aligned}\)       (32)

The output voltage difference between the two branches is:

\(V_{O 1}-V_{O 2}=0\)       (33)

According to the voltage–second balance, when the main switches in each branch of the conventional interleaved boost converter have different duty cycles, the branch with the larger duty cycle can output a higher voltage and operates in the continuous current mode. Meanwhile the other branch automatically operates in the discontinuous current mode.

However, since the two branches of the proposed converter have the cross coupling structure of the capacitors C₁ and C₂, the voltage on the output capacitors series C₃ and C₄ can be automatically adjusted according to the duty cycle of the main switch to achieve a new balance. Therefore, the voltage gain of each branch is equal, which effectively suppresses the ripple of the output voltage.

D. Performance Analysis of the Automatic Suppression of Output Voltage Ripple

In order to facilitate analysis and calculation, the change process of the output capacitances of the two branches can be simplified as a linear change as shown in Fig. 7.

Fig. 7. Output voltage ripple analysis diagram.

At time t₂, the voltage of capacitance and the output voltage can be expressed as:

\(V_{C 3}\left(t_{2}\right)=V_{C 3, a v g}-\frac{(1-d) \Delta V_{C 3}}{2 d}=\frac{2 V_{i n}}{1-d}-\frac{I_{O}(1-d) T_{S}}{2 C_{3}}\)       (34)

\(V_{C 4}\left(t_{2}\right)=V_{C 4, a v g}+\frac{\Delta V_{C 4}}{2}=\frac{2 V_{i n}}{1-d}+\frac{I_{O} d T_{S}}{2 C_{4}}\)       (35)

\(V_{O}\left(t_{2}\right)=V_{C 3}\left(t_{2}\right)+V_{C 4}\left(t_{2}\right)=\frac{4 V_{i n}}{1-d}+\left(\frac{d}{2 C_{4}}-\frac{1-d}{2 C_{3}}\right) I_{O} T_{S}\)       (36)

The expression of the output voltage ripple can be obtained by:

\(\Delta V_{O}=\left|\left(\frac{d}{2 C_{4}}-\frac{1-d}{2 C_{3}}\right)\right| I_{O} T_{S}\)       (37)

E. Analysis of Soft-Start

At first, the converter is started in the open-loop state with an interleaved duty cycle of 0.5 as shown in Fig. 8. When starting the converter, the output logic value of the timer is 0, and the closed-loop is invalid during this time. In this process, the capacitors C₁ and C₄ or C₂ and C₃ are charged like a basic boost converter, and there is no inrush current due to the input inductors. After a certain delay time, which can be designed freely, the output logic value of the timer is 1, and the converter is only operated at the closed-loop as shown in Fig. 8. In addition, there are no inrush currents for the capacitors C_1-4 due to the input inductors.

Fig. 8. Soft start control.

Considering the effect of different delay times, simulated start-up waveforms under different delay times are added as shown in Fig. 9. It can be seen that the capacitors are precharged when the duty cycle is 0.5, and that the inrush current can be restrained to a certain extent due to the existence of inductance.

Fig. 9. Simulated waveforms at start-up with different delay times.

F. Small-Signal Model for Stability Analysis

In order to facilitate modeling analysis, the following assumptions are made. First, the converter works in the CCM. Second, the two inductors are consistent which means inductance L₁=L₂.

The state variables are selected as:

\(x^{T}=\left[\begin{array}{llll} i_{L 1} & i_{L 2} & V_{C 1} & V_{C 2} & V_{C 3} & V_{C 4} \end{array}\right], \quad v=\left[\begin{array}{l} V_{i n} \\ \end{array}\right].\)

One cycle of the converter can be divided into three states. In each mode of operation, the circuit is linear and its behavior can easily be described by the state-space model given by:

\(\left\{\begin{array}{ll} \dot{x}=A_{i} x+B_{i} \\ y=C_{i} x & \end{array}\right. i=1,2,3\)       (38)

\(\begin{array}{l} A_{1}=\left[\begin{array}{cccccc} \frac{-r_{L 1}}{L_{1}} & 0 & 0 & 0 & 0 & 0 \\ 0 & \frac{-r_{L 2}}{L_{2}} & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} \\ 0 & 0 & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} \end{array}\right]\\ \begin{array}{l} B_{1}^{T}=\left[\begin{array}{lllllllll} 1 / L_{m 1} & 1 / L_{m 2} & 0 & 0 & 0 & 0 \end{array}\right] \\ C_{1}=\left[\begin{array}{llllll} 0 & 0 & 0 & 0 & 1 & 1 \end{array}\right] & \end{array} \end{array}\)       (39)

\(\begin{array}{l} A_{2}=\left[\begin{array}{ccccc} \frac{-r_{L 1}}{L_{1}} & 0 & 0 & 0 & 0 & 0 \\ 0 & \frac{2 r_{L 2}+r_{c 1}}{2 L_{2}} & \frac{1}{L_{2}} & 0 & 0 & 0 \\ 0 & \frac{1}{2 C_{1}} & 0 & 0 & 0 & 0 \\ 0 & \frac{-1}{2 C_{2}} & 0 & 0 & 0 & 0 \\ 0 & \frac{-r_{c 4}}{2\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} \\ 0 & \frac{R+r_{c 3}}{2\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & \left.\frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}}\right] \end{array}\right.\\ \begin{array}{l} B_{2}^{T}=\left[\begin{array}{lllllll} 1 / L_{1} & 1 / L_{2} & 0 & 0 & 0 & 0 \end{array}\right] \\ C_{2}=\left[\begin{array}{llllll} 0 & 0 & 0 & 0 & 1 & 1 \end{array}\right] & \end{array} \end{array}\)       (40)

\(\begin{array}{l} A_{3}=\left[\begin{array}{cccccc} \frac{2 r_{L 1}+r_{c 2}}{2 L_{1}} & 0 & 0 & \frac{-1}{L_{1}} & 0 & 0 \\ 0 & \frac{-r_{L2}}{L_{2}} & 0 & 0 & 0 & 0 \\ \frac{-1}{2 C_{1}} & 0 & 0 & 0 & 0 & 0 \\ \frac{1}{2 C_{2}} & 0 & 0 & 0 & 0 & 0 \\ \frac{R+r_{c 4}}{2\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & 0 & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} \\ \frac{-r_{c 3}}{2\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & 0 & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} \end{array}\right] \\ \begin{array}{l} B_{3}^{T}=\left[\begin{array}{lllllll} 1 / L_{1} & 1 / L_{2} & 0 & 0 & 0 & 0 \end{array}\right] \\ C_{3}=\left[\begin{array}{llllll} 0 & 0 & 0 & 0 & 1 & 1 \end{array}\right] & \end{array} \end{array}\)       (41)

In the expressions, r_L1, r_L2, r_C1 ~ r_C4 are the parasitic resistors for the inductors (L₁ and L₂) and capacitors (C₁ ~ C₄), respectively. When S₁ and S₂ are switched on, the state-space equation can be expressed as equation (39). After the main switch S₂ is turned off, S₁ is still on, and the state-space equation is expressed as equation (40). When S₁ is turned off, S₂ is on, and the state-space equation is expressed as equation (41).

According to the duty ratios of the three switching states, the following operations are performed.

\(\left\{\begin{array}{l} A=(2 d-1) A_{1}+(1-d) A_{2}+(1-d) A_{3} \\ B=(2 d-1) B_{1}+(1-d) B_{2}+(1-d) B_{3} \\ C=(2 d-1) C_{1}+(1-d) C_{2}+(1-d) C_{3} \end{array}\right.\)       (42)

The state-space averaging equations are obtained as equation (43).

\(\begin{array}{l} A=\left[\begin{array}{cccccc} \frac{(2-4 d) r_{L1}+(1-d) r_{c 2}}{2 L_{1}} & 0 & 0 & \frac{1-d}{L_{1}} & 0 & 0 \\ 0 & \frac{(2-4 d) r_{L2}+(1-d) r_{c 1}}{2 L_{2}} & \frac{1-d}{L_{2}} & 0 & 0 & 0 \\ \frac{d-1}{2 C_{1}} & \frac{1-d}{2 C_{1}} & 0 & 0 & 0 & 0 \\ \frac{1-d}{2 C_{2}} & \frac{d-1}{2 C_{2}} & 0 & 0 & 0 & 0 \\ \frac{(1-d)\left(R+r_{c4}\right)}{2\left(R+r_{c3}+r_{c 4}\right) C_{3}} & \frac{(d-1)r_{c4}}{2\left(R+r_{c3}+r_{c 4}\right) C_{4}} & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{3}} \\ \frac{(d-1)r_{c3}}{2\left(R+r_{c3}+r_{c 4}\right) C_{4}} & \frac{(1-d)\left(R+r_{c3}\right)}{2\left(R+r_{c3}+r_{c 4}\right) C_{3}} & 0 & 0 & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} & \frac{-1}{\left(R+r_{c 3}+r_{c 4}\right) C_{4}} \end{array}\right] \\ \begin{array}{l} B=\left[\begin{array}{lllllll} 1 / L_{1} & 1 / L_{2} & 0 & 0 & 0 & 0 \end{array}\right] \\ C=\left[\begin{array}{llllll} 0 & 0 & 0 & 0 & 1 & 1 \end{array}\right] \end{array} \end{array}\)       (43)

By adding small signal perturbations, that is \(X=x+\hat{x}\), \(V=v+\hat{v}\), \(D=d+\hat{d}\), \(Y=y+\hat{y}\) and \(\hat{x} \ll x\), \(\hat{d} \ll d\), \(\hat{v} \ll v\), \(\hat{y} \ll y\), the small-signal state-space expression of the converter can be obtained by eliminating the DC terms.

\(\left\{\begin{array}{l} \dot{X}=A X+B X+E D \\ Y=C X \end{array}\right.\)       (44)

Where E = (2A₁ - A₂ - A₃)x + (2B₁ - B₂ - B₃)v.

The main design parameters of the converter are: input voltage V_in=24V, output voltage V_o=200V, output power P_o=200W, switching frequency f=100kHz, duty cycle d=0.6, coupling inductance turn ratio n=1, excitation inductor L₁=L₂=100uH, and capacitances C₁=C₂=47uF, C₃= C₄= 100uF.

The expression of the open loop transfer function is:

\(\begin{aligned} T_{v}(s)=& \frac{0.102\left(s-1.159 \times 10^{4}\right)\left(s+1.375 \times 10^{4}\right)}{\left(s^{2}+7.84 s+1.65 \times 10^{4}\right)} \\ & \times \frac{\left(s^{2}-1.317 s+1.97 \times 10^{6}\right)}{\left(s^{2}-3.35 s+1.019 \times 10^{6}\right)} \end{aligned}\)       (45)

A frequency response bode plot is obtained from (45) as shown in Fig. 10.

Fig. 10. Bode diagram of a system without compensation.

If the compensator is not introduced into a system, it can be seen from Fig. 10 that the amplitude margin of the system is infinity, the phase angle margin is 91.3° and the cut-off frequency is 339Hz. The system has a positive phase margin, indicating that the system is stable. However, the phase margin is smaller and the stability is poor.

After the compensator was added, the expression of closed-loop transfer function is as follows:

\(\begin{aligned} T_{v}(s)=& \frac{12.24(0.01 s+1)(0.0131 s+1)\left(s-1.159 \times 10^{4}\right)}{s\left(0.25 \times 10^{-3} s+1\right)\left(s^{2}+7.84 s+1.65 \times 10^{4}\right)} \\ & \times \frac{\left(s+1.375 \times 10^{4}\right)\left(s^{2}-1.317 s+1.97 \times 10^{6}\right)}{\left(s^{2}-3.35 s+1.019 \times 10^{6}\right)} \end{aligned}\)       (46)

The frequency response bode plot is obtained from (46) as shown in Fig. 11.

Fig. 11. Bode diagram of a system with compensation.

It can be seen from Fig. 11 that the phase margin of the system is increased to 44.7, the amplitude margin is 9.49 dB and the cut-off frequency is 1.4 kHz after the PID compensator is added. From the above parameters, it can be seen that the stability of the system is improved after adding the PID compensator, and the gain margin is kept within the appropriate range. At the same time, the ability of the system to resist input voltage disturbances and load disturbances is greatly enhanced.

IV. PERFORMANCE OF COMPARISON

A performance of comparison among the interleaved converters published in [12], [16], [19] and the proposed converter is shown in Table I.

TABLE I PERFORMANCE COMPARISON OF DIFFERENT CONVERTERS

When compared with the converter in [12], the proposed converter doubles the gain while only adding one diode and one capacitor. It also has lower voltage stress and output voltage ripple than the converter in [12]. The converter in [19] achieved a higher voltage gain and soft switching through a coupled inductance technology. However, active or passive clamping circuits are needed to reduce the voltage spikes caused by leakage inductance. The large number of devices reduces the efficiency and is not conducive to improving the power density of the converter. In comparison, the proposed converter has a similar voltage gain, voltage stress and low output voltage ripple while using fewer devices. It is favorable in terms of reliability, circuit volume and cost. Therefore, the proposed converter is a good alternative for applications that require an ultra-step-up voltage gain and a high reliability.

V. DESIGN CONSIDERATIONS

A. Inductor Design

The inductors L₁ and L₂ can be obtained by:

\(L_{B}=\frac{d(1-d)^{2} R}{8 f_{S}}\)       (47)

If the converter is operated in the CCM operation, the inductors L₁ and L₂ should be larger than L_B.

B. Capacitor Design

The capacitor design mainly aims to keep the voltage stresses and fluctuations of the voltage at both ends of the capacitor to within a certain range. The capacitance can be selected by the following formula as:

\(C \geq \frac{P_{\max }}{2 \cdot V_{O} \cdot \Delta V_{C} \cdot f_{s}}\)       (48)

VI. EXPERIMENTAL RESULTS

An experimental prototype circuit of the presented converter is built and tested in the laboratory in order to verify the validity of the theoretical analysis. The components used in the converter are shown in Table II.

TABLE II PROTOTYPE COMPONENTS AND PARAMETERS

Figs. 12(a) and 12(b) show waveforms of the currents of the inductors L₁ and L₂ and the input current i_in. It can be seen that the currents i_L1 and i_L2 are nearly same, and that the input current ripples are very low (ripple rate about 7%) due to the interleaved operation. The theoretical current ripple rate of i_in is 5%, which agrees with the experimental result.

Fig. 12. Waveforms of the currents of inductors.

Fig. 13 shows the currents of the main switches S₁ and S₂ and the diodes D₁~D₄. Fig. 13(c) shows that the current waveforms and the peak values of the two switches are basically equal. Combined with the current waveforms of the inductors L₁ and L₂ in Fig. 12, it can be concluded that the proposed converter has a better automatic current sharing function.

Fig. 13. Current waveforms of the main switches and diodes.

Figs. 14(a) and 14(b) show waveforms of the voltage stress and current stress of the switches S₁ and S₂ at an output voltage of 200V. Thus, MOSFETs with low on-resistance and low voltage levels can be used. It is useful to reduce the switching losses and to improve efficiency.

Fig. 14. Waveforms of the voltage current stress of switches.

Fig. 15(a) and 15(b) show the voltage stresses on the diodes D₁, D₂, D₃ and D₄. It can be seen that the voltage stresses of the diodes D₁, D₂, D₃ and D₄ are approximately 100 V, which is equal to half of the output voltage in the steady-state period.

Fig. 15. Waveforms of the voltage stress on diodes.

Fig. 16(a) shows the output voltages of the two branches when the main switch duty cycles are d₁=0.65 and d₂=0.6. Fig. 16(b) shows the output voltages of the two branches when the duty cycles are d₁=0.7 and d₂=0.6. According to the Fig. 16(a) and 16(b) it can be found that the output voltages of the two branches are always equal, even if the main switch duty ratios are different. The correctness of the theoretical analysis of the automatic balancing of the two branch output voltages is verified.

Fig. 16. Output voltages of the two branches at different duty cycles.

Fig. 17(a) shows a soft-start with a too long delay time. Fig. 17(b) shows a soft-start with an appropriate delay time. It can be seen that the different delay times have an obvious influence on the soft-start performance. When the setting of the delay time is appropriate, it can achieve a better soft start effect.

Fig. 17. Waveforms at start-up with different delay times.

Fig. 18 shows a dynamic response between 200 W and 135 W due to a (200Ω-300Ω-200Ω) step load variation, and the output voltage is maintained at 200V.

Fig. 18. Experimental waveforms of a step load.

Fig. 19 shows the experimental conversion efficiency of the proposed converter when the switching frequency is 100k. The measured maximum efficiency is about 94.37% at half load. When the output power is low, the decrease in efficiency is due to wire loss, drive loss and constant loss.

Fig. 19. Efficiency of the proposed converter.

VII. CONCLUSION

This paper has successfully developed a novel high voltage gain DC–DC converter for low voltage renewable energy systems such as photovoltaic applications. The working principle and steady-state characteristics of the converter are analyzed in detail, and an experimental platform has been developed and tested. The measured maximum efficiency is about 95.7% at half load.

The proposed converter can achieve a high step-up voltage gain and reduce the voltage stress of both the active switches and the diodes, which allows for the use of lower voltage rating MOSFETs and diodes to reduce both the switching and conduction losses. Other characteristics of the converter are: a low output-voltage ripple and a low input-current ripple, which can prevent accelerated reductions it the lifetime of a photovoltaic cell and load. In addition, due to the charge balance of the blocking capacitor, the converter features automatic voltage sharing between C₃ and C₄ without adding any extra circuitry or complex control methods.