그림 1. Voltage mode class D 전력증폭기 회로 Fig. 1. Voltage mode class D power amplifier circuit.
그림 2. Current mode class D 전력증폭기의 회로 Fig. 2. Current mode class D power amplifier circuit
그림 3. 설계된 16 W급 전류모드 D급 전력증폭기 회로도 Fig. 3. A schematic diagram of the 16 watt CMCD power amplifier.
그림 4. 입력전력에 따른 PAE, Pout 시뮬레이션 Fig. 4. PAE and Pout simulation according to input power
그림 5. FET1 드레인 전압과 전류의 파형 시뮬레이션 Fig. 5. Simulated waveform of FET1 drain voltage and current.
그림 6. 로드 임피던스 변화에 따른 전력부가효율 및 출력전력 Fig. 6. Power added efficiency and output power due to load impedance change.
그림 7. 제작된 16 W 전류 모드 D급 전력증폭기 Fig. 7. Implemented 16 watt CMCD power amplifier.
그림 8. 입력전력에 따른 PAE, Pout 측정값 Fig. 8. PAE and Pout measurement according to input power.
그림 10. Rload 변화에 따른 PAE, 출력 전력 Fig. 10. PAE, load variation with output power.
그림 9. 제작된 60x80 mm2 송신 및 수신 코일 Fig. 9. Manufactured 60x80 mm2 transmit and receive coils.
표 1. 송수신 코일 20 mm간격에서의 x축 변화량에 따른 S11 Table 1. S11 according to x-axis variation with 20mm separation of Tx and Rx coils.
표 2. 송수신 코일 20 mm간격에서의 y축 변화량에 따른 S11 Table 2. S11 according to y-axis variation with 20mm separation of Tx and Rx coils.
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