The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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A Development of JPEG-LS Platform for Mirco Display Environment in AR/VR Device.

AR/VR 마이크로 디스플레이 환경을 고려한 JPEG-LS 플랫폼 개발

  • 박현문 (전자부품연구원 SoC 플랫폼 연구센터) ;
  • 장영종 (전자부품연구원 SoC 플랫폼 연구센터) ;
  • 김병수 (전자부품연구원 SoC 플랫폼 연구센터) ;
  • 황태호 (전자부품연구원, SoC 플랫폼연구센터)
  • Received : 2018.12.13
  • Accepted : 2019.04.15
  • Published : 2019.04.30
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Abstract

This paper presents the design of a JPEG-LS codec for lossless image compression from AR/VR device. The proposed JPEG-LS(: LosSless) codec is mainly composed of a context modeling block, a context update block, a pixel prediction block, a prediction error coding block, a data packetizer block, and a memory block. All operations are organized in a fully pipelined architecture for real time image processing and the LOCO-I compression algorithm using improved 2D approach to compliant with the SBT coding. Compared with a similar study in JPEG-LS, the Block-RAM size of proposed STB-FLC architecture is reduced to 1/3 compact and the parallel design of the predication block could improved the processing speed.

AR/VR 디바이스에서 무손실 이미지 압축을 위한 JPEG-LS(: LosSless) 코덱에서 SBT 기반 프레임 압축기술로 메모리와 지연을 줄이는 설계를 제안하였다. 제안된 JPEG 무손실 코덱은 주로 콘텍스트 모형화 및 업데이트, 픽셀과 오류 예측 그리고 메모리 블록으로 구성된다. 모든 블록은 실시간 영상처리를 위해 파이프라인 구조를 가지며, LOCO-I 압축 알고리즘에 SBT 코딩기반의 개선된 2차원 접근방식을 사용한다. 제시한 STB-FLC기법을 통해 Block-RAM 사이즈를 기존 유사연구보다 1/3로 줄이고 예측(prediction) 블록의 병렬 설계는 처리속도에 향상을 가져올 수 있었다.

Keywords

KCTSAD_2019_v14n2_417_f0001.png 이미지

그림 1. JPEG-LS 블록 다이어그램 Fig. 1 JPEG-LS block diagram

KCTSAD_2019_v14n2_417_f0002.png 이미지

그림 2. 모듈러 처리의 지역 기울기와 양자화 Fig. 2 Local gradients and quantization on the modeler

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그림 4. STB기반에 추가된 FLC 구조 Fig. 4 The FLC structure added to the STB based

KCTSAD_2019_v14n2_417_f0005.png 이미지

그림 5. 설계된 예측 블록 Fig. 5 Design of the prediction block

KCTSAD_2019_v14n2_417_f0006.png 이미지

그림 6. 콘텍스트 업데이트와 연결된 메모리 블록 Fig. 6 Context update and memory block

KCTSAD_2019_v14n2_417_f0007.png 이미지

그림 7. 구현된 FPGA에 합성 결과의 비교 Fig. 7 Comparison of synthesis results on implemented FPGA

KCTSAD_2019_v14n2_417_f0008.png 이미지

그림 8. 알고리즘 압축률(bpp)의 비교 Fig. 8 Compression rates(bpp) of algorithm

KCTSAD_2019_v14n2_417_f0009.png 이미지

그림 3. 개발한 JPEG-LS 구조 Fig. 3 Development of the JPEG-LS

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