The Transactions of the Korean Institute of Power Electronics (전력전자학회논문지)

The Korean Institute of Power Electronics (전력전자학회)
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Development of Leakage Current Reduction Method in 3-Level Photovoltaic PCS

3레벨 태양광 PCS에서의 누설전류 저감기법 개발

  • Han, Seongeun (Dept. of Electrical Engineering, Chungnam National University) ;
  • Jo, Jongmin (Dept. of Electrical Engineering, Chungnam National University) ;
  • An, Hyunsung (Dept. of Electrical Engineering, Chungnam National University) ;
  • Cha, Hanju (Dept. of Electrical Engineering, Chungnam National University)
  • Received : 2018.09.18
  • Accepted : 2018.10.26
  • Published : 2019.02.20
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Abstract

In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a $1{\mu}F$ parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method.

Keywords

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Fig. 1. Configuration of the 3-phase 3-level NPC-type inverter system.

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Fig. 4. Comparison of PWM method.

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Fig. 5. PSIM simulation.

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Fig. 6. Simulation result for comparison of conventional PWM with proposed PWM.

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Fig. 7. Configuration of experiment.

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Fig. 8. Experiment result for comparison of conventional PWM with proposed PWM.

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Fig. 2. Common mode voltage equivalent circuit.

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Fig. 3. Space vector diagram of 3-level inverter.

TABLE I COMMON MODE VOLTAGE ACCORDING TO VOLTAGE VECTOR

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TABLE II SYSTEM PARAMETER

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