전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제68권1호
  • /
  • Pages.90-97
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  • 2019
  • /
  • 1975-8359(pISSN)
  • /
  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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직렬 커패시터 D/A 변환기를 갖는 저전력 축차 비교형 A/D 변환기

Low Power SAR ADC with Series Capacitor DAC

  • Lee, Jeong-Hyeon (Dept. of Electronic Engineering, Chonbuk National University) ;
  • Jin, Yu-Rin (Dept. of Electronic Engineering, Chonbuk National University) ;
  • Cho, Seong-Ik (Dept. of Electronic Engineering, Chonbuk National University)
  • 투고 : 2018.08.31
  • 심사 : 2018.12.17
  • 발행 : 2019.01.01
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초록

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

키워드

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그림 1 전하 재분배 DAC를 이용한 SAR ADC Fig. 1 SAR ADC using charge redistribution DAC

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그림 2 전하 재분배 DAC의 출력 Fig. 2 Output of the charge redistribution DAC

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그림 3 커패시터들의 직렬연결을 이용한 직렬 커패시터 DAC Fig. 3 Series capacitor DAC using series connection of capacitors

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그림 4 전치 증폭기를 가지는 동적 비교기 Fig. 4 Dynamic comparator with preamplifier

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그림 5 제안하는 6-bit SAR ADC를 위한 직렬 커패시터 DAC의 제어 신호들 Fig. 5 Control signals of the series capacitor DAC for proposed 6-bit SAR ADC

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그림 6 중첩된 제어 신호의 예시 Fig. 6 Example of overlapped control signals

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그림 7 중첩된 제어 신호가 인가된 직렬 커패시터 DAC의 동작 Fig. 7 Operation of the series capacitor DAC withoverlapped control signals applied

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그림 8 동적 특성 모의실험을 위한 전력 스펙트럼 밀도 Fig. 8 PSD for dynamic characteristics simulation

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그림 9 DNL과 INL의 모의실험 결과 Fig. 9 Simulation results of DNL and INL

표 1 제안하는 SAR ADC와 이전 연구들의 성능 비교 Table 1 Comparison of performance between proposed SAR ADC and previous studies

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표 2 DAC에 따른 단위 커패시터의 수 비교 Table 2 Comparison of the number of unit capacitors according to the DAC

DHJGII_2019_v68n1_90_t0002.png 이미지

참고문헌

  1. Qianying Tang, Won Ho Choi, Luke Everson, Keshab K. Parhi and Chris H. Kim, "A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC", 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
  2. Yusuke Tsukamoto, Koji Obata, Kazuo Matsukawa, Koji Sushihara, "High Power Efficient and Scalable Noise-Shaping SAR ADC for IoT Sensors", 2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), pp. 1-2, June 2016.
  3. Ming Ding, Guibin Chen, Pieter Harpe, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips, Arthur van Roermund, "A Circuit-Design-Driven Tool With a Hybrid Automation Approach for SAR ADCs in IoT", 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 672-675, March 2018.
  4. Khuram Shehzad, Hye-Young Kang, Deeksha Verma, Young Jun Park, Kang-Yoon Lee, "Low-Power 10-Bit SAR ADC using Class-AB type Amplifier for IoT Applications", 2017 International SoC Design Conference (ISOCC), pp. 224-225, November 2017.
  5. Hao-Chiao Hong, Yi Chiu, "A 0.20-V to 0.25-V, SubnW, Rail-to-Rail, 10-Bit SAR ADC for Self-Sustainable IoT Applications", 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2018.
  6. S. Meguellati, N. E. Bouguechal, R. Arnold, O. Manck "A Charge Redistribution SAR ADC for a Pressure Correction ASIC", 2005 12th IEEE International conference on Electronics, Circuits and Systems, pp. 1-4, December 2005.
  7. A. J. C. Lanot, T. R. Balen, "Reliability Analysis of a 130nm Charge Redistribution SAR ADC under Single Event Effects", 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1-7, December 2014.
  8. Xiucheng Zhou, Ying Zhang, Yun Su, "An 8-bit 35-MS/s successive approximation register ADC", 2015 IEEE International Conference on Progress in Informatics and Computing (PIC), pp. 531-533, December 2015.
  9. Yi-Long Yu, Fu-Chen Huang, Chorng-Kuang Wang, "A 1V 10-Bit 500KS/s Energy-Efficient SAR ADC Using Master-Slave DAC Technique in 180nm CMOS", Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, pp. 1-4, April 2014.
  10. Xingyuan Tong, Zhangming Zhu, Yintang Yang, "Lowpower Capacitor Arrays for Charge Redistribution SAR A/D Converter in 65nm CMOS", 2009 Pacific-Asia Conference on Circuits, Communications and Systems, pp. 293-296, September 2009.
  11. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure", IEEE Journal of Solid-State Circuits, Vol. 45, No 4, pp. 731-740, March 2010. https://doi.org/10.1109/JSSC.2010.2042254
  12. Neil H. E. Weste, David Money Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Pearson, 2011.
  13. Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, Chorng-Kuang Wang "A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications", 2009 IEEE Asian Solid-State Circuits Conference, pp. 149-152, November 2009.
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