그림 1.재구성 가능한 프로세서의 구조 Fig. 1. Architecture of the Reconfigurable Processor
표 1. 메모리처리단의 성능 Table I. Performance of Memory Processing Unit
표 2. 캐시 크기에 따른 캐쉬 히트 비율과 메모리 대역폭 Table 2. Cache hit ratio and Memory bandwidth according to cache size
표 3. 압축률과 압축표준에 따른 캐시 히트율과 대역폭 Table 3. Cache hit ratio and Bandwidth according to compression ratio and compression standard
표 4. 병렬처리를 위한 비디오 복호기의 기능들 Table 4. Video decoder functions for Parallel processing
References
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