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Numerical Analysis of Thermal Deformation of a PCB for Semiconductor Package at Panel, Strip and Unit Levels

수치해석을 이용한 판넬과 스트립 및 유닛 레벨 반도체 패키지용 PCB의 열변형 해석

  • Cho, Seunghyun (Mechanical Engineering Department, Dongyang Mirae University) ;
  • Ko, Youngbae (Molds & Dies Technology R&BD Group, KITECH)
  • 조승현 (동양미래대학교 기계공학과) ;
  • 고영배 (한국생산기술연구원 금형기술그룹팀)
  • Received : 2019.10.28
  • Accepted : 2019.12.14
  • Published : 2019.12.30

Abstract

In this study, we conducted numerical analyses using the Taguchi method and finite element method to calculate the thermal deformation of a printed circuit board and the effect of design factors on the thermal deformation. Analysis results showed that the thermal deformation of the panel had the strongest effect on the thermal deformation and shape of the strip and unit. In particular, the deformation in the z direction was larger than that in the xy-plane direction. The effect of design factors and the design conditions for reducing the thermal deformation of the panel and strip changed at the unit level. Therefore, it is recommended that panel-level thermal deformation must be controlled to reduce the final thermal deformation at the unit level because the thermal deformation of the strip strongly affects that of the unit.

본 논문에서는 다구찌법과 유한요소법의 수치해석을 통해 인쇄회로기판의 열변형과 열변형에 미치는 설계인자의 영향도를 계산하였다. 인쇄회로기판의 패널과 스트립 레벨은 큐어링 온도조건에서, 유닛 레벨은 리플로우 온도조건에서 수치해석을 수행하였다. 해석결과에 따르면 패널의 열변형이 스트립과 유닛의 열변형량과 형상에 가장 큰 영향을 미치며, 특히 z방향 변형량이 xy평면 방향의 변형량보다 크게 발생하였다. 열변형에 대한 설계인자의 영향도 분석 결과에 의하면 열변형을 줄이기 위한 설계인자들의 영향도와 설계조건이 패널, 스트립과 유닛 레벨에 따라 달라지기 때문에 반도체 패키지의 신뢰성 향상을 목적으로 유닛 레벨의 열변형을 제어하기 위해서는 패널 레벨의 열변형을 제어할 필요가 있고 인쇄회로기판의 층별 두께는 설계인자 수준의 중간으로 선정하는 것이 필요하다.

Keywords

References

  1. M. A. Bolanos, "Semiconductor IC Packaging Technology Challenges : The Next Five Years", SPAY025, EMAP2005 (Texas Instruments), (2005).
  2. X. J. Fan, B. Varia, and Q. Han, "Design and optimization of thermo-mechanical reliability in wafer level packaging", Microelectronics reliab., 50(4), 536 (2010). https://doi.org/10.1016/j.microrel.2009.11.010
  3. R. Darveaux, C. Reichman, and N. Islam, "Interface Failure in Lead Free Solder Joints", Proc. 56th Electronic Components and Technology Conference (ECTC), San Diego, USA, 12, IEEE (2006).
  4. J. H. Lau, and S. W. R. Lee, "Effects of Build-Up Printed Circuit Board Thickness in the Solder Joint Reliability of a Wafer Level Chip Scale Package (WLCSP)", Trans. Comp. Packag. Technol., 25(1), 51 (2002).
  5. M. Y. Tsi, C. H. J. Hsu, and C. T. O. Wang, "Investgation of thermomechanical behaviors of flip chip BGA packages during manufacturing process and thermal cycling", IEEE Trans. Compon. Pack. -Technol., 27(3), 568 (2004). https://doi.org/10.1109/TCAPT.2004.831817
  6. S. H. Cho, S. J. Cho, and J. Lee,"Estimation of warpage and thermal stress of IVHs in flip-chip ball grid arrays package by FEM", Microelectron Reliab., 48, 300 (2008). https://doi.org/10.1016/j.microrel.2007.06.001
  7. R. Darveaux, K. Banerji, A. Mawer, and E. Mammo, "Reliability of Plastic Ball Grid Array Assembly", Ball Grid Array Technology, McGraw-Hill, New York (1995).
  8. J. H. Lau, J. L. Prince, W. Nakayama, and C. P. Wong, "Electronic Packaging: Design, Materials, Process, and Reliability", McGraw-Hill, New York (1997).
  9. E. Lin, D. Chang, D. S. Jiang, Y. P. Wang, and C. S. Hsiao, "Advantage and challenge of coreless Flip chip BGA Microsystems", International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), Taipei, Taiwan, 346, IEEE (2007).
  10. C. Chiu, K. C. Chang, J. Wang, and C. H. Lee, "Challenges of thin core PCB Flip Chip package on advanced Si Nodes", Proc. 57th Electronic Components and Technology Conference (ECTC), 22 (2007).
  11. S. H. Cho, T. E. Chang, J. Lee, and H. P. Park, "New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board", Microelectronics Reliab., 50, 242 (2010). https://doi.org/10.1016/j.microrel.2009.10.009
  12. J. H. Lau, and S.-W.R, Lee, "Effects of Build-Up Printed Circuit Board Thickness in the Solder Joint Reliability of a Wafer Level Chip Scale Package(WLCSP)", Trans. Comp. Packag. Technol., 25(1), 3 (2002). https://doi.org/10.1109/6144.991169
  13. W. Sun, W. H. Zhu, C. K. Wang, A. Y. S. Sun, and H. B. Tan, "Warpage Simulation and DOE Analysis with Application in Package-on-Package Development", Proc. 9th EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems (ESIME), Freiburg im Breisgau, Germany, 244, IEEE (2008).
  14. Y. L. Tzeng, N. Kao, E. Chen, J. Y. Lai, Y. P. Wang, and C. S. Hsiao, "Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure", Proc. 9th Electronics Packaging Technology Conference (EPTC), Singapore, 482, IEEE (2007).
  15. W. Sun, W. H. Zhu, K. S. Le, and H. B. Tan, "Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging", International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Shanghai, 978, IEEE (2008).
  16. S. H. Cho, H. I. Jung, and O. C. Bae, "Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP", J. Microelectron. Packag. Soc., 19(3), 57 (2012). https://doi.org/10.6117/kmeps.2012.19.3.057
  17. S. H. Cho, D. H. Kim, Y. G. Oh, J. T. Lee, and S. S. Cha "A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP", J. Microelectron. Packag. Soc., 22(1), 75 (2015). https://doi.org/10.6117/kmeps.2015.22.1.075
  18. M. S. C. Marc, "Manual Volume A: Theory and User Information", 210 (2015).