Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

Study on Effects of Solder Joint aging on the Reliability of Embedded Package Solder Joints using Numerical analysis

수치해석을 이용한 임베딩 패키지 솔더 조인트의 신뢰성에 미치는 에이징 효과 연구

  • Cho, Seunghyun (Department of Mechanical Engineering, Dongyang Mirae University) ;
  • Jang, Junyoung (Department of Mechanical Engineering, Inha University) ;
  • Ko, Youngbae (Molds & Dies Technology R&D Group, KITECH)
  • 조승현 (동양미래대학교 기계공학과) ;
  • 장준영 (인하대학교 기계공학과) ;
  • 고영배 (한국생산기술연구원 금형기술그룹팀)
  • Received : 2017.11.29
  • Accepted : 2018.03.15
  • Published : 2018.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, the effects of solder joint aging on the reliability of embedded package solder joints were investigated using numerical analysis by finite element method. Solder joints were SAC305 with aging time 0, 60, 180 days. For reliability analysis, warpage of package and equivalent creep strain (ECS) and total strain energy density (TSED) of solder joint were analyzed. The analysis results show that the package warpage is decreased in the case of the embedded package compared to the non embedded package, and the reliability life of the solder joint is predicted to be high. Also, it was interpreted that the longer the aging time, the less the warpage of the embedded package, but the reliability life of the solder joint would be shortened.

본 논문에서는 임베딩 패키지의 솔더 조인트 신뢰성에 미치는 솔더 조인트의 에이징 효과를 유한요소법에 의한 수치해석을 통해 연구하였다. SAC305 솔더 조인트의 에이징 시간은 0, 60, 180 일이 적용되었고 신뢰성 분석을 위해 패키지 휨, ECS(Equivalent Creep Strain) 및 TSED(Total Strain Energy Density)이 분석되었다. 연구결과에 따르면 임베딩 패키지의 휨이 비임베딩 패키지에 비해 감소하여 임베딩 패키지내 솔더 접합부의 신뢰성이 높을 것으로 예측되었다. 또한, 에이징 시간이 길수록 임베디드 패키지의 휨이 감소하지만 솔더 조인트의 신뢰성 수명도 감소할 것으로 분석되었다.

Keywords

References

  1. M. S. K. Rahim, T. Zhou, X. Fan, G. and Rupp, "Board level temperature cycling study of large array wafer level packages", Proc. 59th Electronic Components and Technology Conference (ECTC), USA, 898 (2009).
  2. V. S. Milena, "Thermally induced deformations in die-substrate assembly", Theoret. Appl. Mech., 35(1-3), 305 (2008). https://doi.org/10.2298/TAM0803305V
  3. L. Wetz, J. White, and B. Keser, "Improvement in WL-CSP Reliability by Wafer Thinning", Proc. Electronic Components and Technology Conference (ECTC), 853, IEEE (2003).
  4. A. Yeo, and C. Lee, "Flip Chip Solder Joint Reliability Analysis Using Viscoplastic and Elastic-Plastic-Creep Constitutive Models", IEEE Trans. On Comp. and Packag Tech., 29(2), 355 (2006). https://doi.org/10.1109/TCAPT.2006.875893
  5. C. S. Lau, M. Z. Abdullah, M. A. Mujeebu, N. M. D. Yusop, "Finite element analysis on the effect of solder joint geometry for the reliability of ball grid array assembly with flexible and rigid PCBs", Journal of Engineering Science and Technology, 9(1), 47 (2014).
  6. L. Anand, "Constitutive Equations for the Rate-Dependent Deformation of Metals at Elevated Temperatures", Journal of Engineering Materials and Technology, Transactions of the ASME., 104(1), 12 (1982). https://doi.org/10.1115/1.3225028
  7. C. M. Hsu, A. D. Lin, J. H. and Kuang, "The Creep Parameters of SAC305 Unleaded Solders", Advances in Materials Science and Engineering, 1 (2013).
  8. G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, "Applying Anand Model to Represent the Viscoplastic Deformation Behavior of Solder Alloys", Journal of Electronic Packaging, 123, 247 (2001). https://doi.org/10.1115/1.1371781
  9. L. Zhang, Z. Liu, and Y. Ji, "Anand constitutive model of lead-free solder joints in 3D IC device", Journal of Physics: Conference Series, 738, 1 (2016).
  10. M. Motalab, "Determination of Anand constants for SAC Solders using Stress-Strain or Creep Data", Proc. 13th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), San Diego, 910 (2012).
  11. L. Zhang, Z. Q. Liu, and Y. T. Ji, "Anand constitutive model of lead-free solder joints in 3D IC device", Journal of Physics: Conference Series, 738(1), 012050 (2016). https://doi.org/10.1088/1742-6596/738/1/012050
  12. G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, "Applying Anand Model to Represent the Viscoplastic Deformation Behavior of Solder Alloys", Journal of Electronic Packaging, 123(3), 247 (2001). https://doi.org/10.1115/1.1371781
  13. L. Boettcher, S. Karaszkiwicz, D. Manessis, and A. Ostmann, "Embedded chip technology: Technologies, applications, and future developments", Proc. Additional Papers and Presentations, San Diego, 001223 (2012).
  14. C. T. Ko, S. Chen, C. W. Chiang, T. Y. Kuo, Y. C. Shih, and Y. H. Chen, "Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP", Proc. 56th Electronics Components and Technology Conference (ECTC), San Diego, 322, IEEE (2006).
  15. L. Boettcher, D. Manessis, A. Ostmann, and H. Reichel, "Realization of system in package modules by embedding of chips", Proc. IMAPS Device Packaging, Scottsdale, 397 (2008).
  16. H. W. Park, S. H. Cho, J. Kress, A. Bruderer, and N. Galster, "Dielectric composite material with good performance and process ability for embedding of active and passive components into PCBs", Proc. 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, 1325, IEEE (2013).
  17. S. H. Cho, D. H. Kim, Y. G. Oh, J. T. Lee, and S. S. Cha, "A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP", J. Microelectron. Packag. Soc., 22(1), 75 (2015). https://doi.org/10.6117/kmeps.2015.22.1.075
  18. D. H Park, and T. S Oh, "Reliability Characteristics of a Package- on-Package with Temperature/Humidity Test, Temperature Cycling Test, and High Temperature Storage Test", J. Microelectron. Packag. Soc., 23(3), 43 (2016). https://doi.org/10.6117/KMEPS.2016.23.3.043
  19. X. J. Fan, B. Varia, and Q. Han, "Design and optimization of thermo-mechanical reliability in wafer level packaging", Microelectronics Reliability, 50, 536 (2010). https://doi.org/10.1016/j.microrel.2009.11.010
  20. M. Motalab, "A Constitutive Model for Lead Free Solder Including Aging Effects and Its Application to Microelectronic Packaging", Degree of Doctor of Philosophy, Auburn University, 134 (2013).