Journal of information and communication convergence engineering

  • 제16권1호
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  • Pages.43-47
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  • 2018
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  • 2234-8255(pISSN)
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  • 2234-8883(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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Analysis of Flat-Band-Voltage Dependent Breakdown Voltage for 10 nm Double Gate MOSFET

  • Jung, Hakkee (Department of Electronic Engineering, Kunsan National University) ;
  • Dimitrijev, Sima (Griffith School of Engineering, Griffith University)
  • 투고 : 2017.09.22
  • 심사 : 2017.10.25
  • 발행 : 2018.03.31
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초록

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

키워드

E1ICAW_2018_v16n1_43_f0001.png 이미지

Fig. 1. Schematic diagram of a double gate MOSFET with potential energy

E1ICAW_2018_v16n1_43_f0002.png 이미지

Fig. 2. Potential energy distribution along the y-axis for the increasing flat-

E1ICAW_2018_v16n1_43_f0003.png 이미지

Fig. 3. (a) Drain current？voltage characteristics and (b) contributions of

E1ICAW_2018_v16n1_43_f0004.png 이미지

Fig. 4. Breakdown voltages for the intrinsic-body and doped-body

E1ICAW_2018_v16n1_43_f0005.png 이미지

Fig. 5. Breakdown voltages for different silicon thicknesses of undoped

Table 1. Possible silicon thickness to oxide thickness for breakdownvoltage above 1.5 V

E1ICAW_2018_v16n1_43_t0001.png 이미지

참고문헌

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피인용 문헌

  1. Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region vol.9, pp.18, 2019, https://doi.org/10.3390/app9183716
  2. Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices vol.10, pp.13, 2018, https://doi.org/10.3390/app10134475