전력전자학회논문지 (The Transactions of the Korean Institute of Power Electronics)

  • 제23권6호
  • /
  • Pages.415-423
  • /
  • 2018
  • /
  • 1229-2214(pISSN)
  • /
  • 2288-6281(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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고정 샘플링 주파수에서의 모듈형 멀티레벨 컨버터 레벨 선택 알고리즘

Level Selection Algorithm with Fixed Sampling Frequency for Modular Multilevel Converter

  • Kim, Chan-Ki (Power Transmission Laboratory, KEPCO Research Institut) ;
  • Park, Chang-Hwan (Dept. of Electrical Eng., Pusan National University) ;
  • Kim, Jang-Mok (Dept. of Electrical Eng., Pusan National University)
  • 투고 : 2018.07.20
  • 심사 : 2018.10.01
  • 발행 : 2018.12.20
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초록

This study uses a level selection algorithm with fixed sampling frequency for modular multilevel converter (MMC) systems. Theoretically, the proposed method increases the level infinitely while the sampling time remains the same. The proposed method called cluster stream buffer (CSB) consists of several clusters, wherein each cluster is composed of 32 submodules that depend on the level of the submodules in the MMC system. To increase the level of the MMC system, additional clusters are used, and the sampling time between clusters is determined from the sampling time between levels needed for utilizing the entire level from the MMC system. This method is crucial in the control of MMC-type HVDC systems because it improves scalability and precision.

키워드

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Fig. 1. Basic structure of MMC.

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Fig. 2. ABB’S Group Module based MMC.

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Fig. 3. Pole voltage of ABB’s MMC using group module topology.

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Fig. 4. Single-phase equivalent circuit of MMC.

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Fig. 5. MMC Control Diagram with NLC Modulation.

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Fig. 6. Output voltage of NLC with small sampling interval.

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Fig. 8. Actual implementation of the proposed “Cluster stream buffer” method for MMC.

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Fig. 7. Output voltage of NLC with large sampling interval.

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Fig. 9. Cluster module based MMC arm.

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Fig. 10. Cluster module based MMC controller H/W structure.

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Fig. 11. Output voltage level of MMC based VSC-HVDC without cluster stream buffer method.

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Fig. 12. Output voltage level of MMC based VSC-HVDC using cluster stream buffer method.

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Fig. 13. Simulation result of the proposed algorithm: Cluster stream buffer.

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Fig. 14. Simulation result of conventional method. (a) Upper and lower arm voltages, (b) Three phase output current.

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Fig. 15. Simulation result of proposed method. (a) Upper and lower arm voltages, (b) Three phase output current.

TABLE I SIMULATION PARAMETER OF GRID CONNECTEDMMC SYSTEM

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참고문헌

  1. R. Marquardt, "Stromrichterschaltungen mit verteilten energiespeichern," German Patent DE 10103031A1, Jan. 24, 2001.
  2. A. Lesnicar and R. Marquardt, "An innovative modular multilevel converter topology suitable for a wide power range," in Proc. IEEE Power Tech Conf., Bologna, Italy, pp. 6, 2003.
  3. A. Lesnicar and R. Marquardt, "A new modular voltage source inverter topology," presented at the EPE, Toulouse, France, Sep. 2003.
  4. J. Dorn, H. Huang, and D. Retzmann, "A new multilevel voltage sourced converter topology for HVDC applications," in CIGRE Session, Paris, France, 2008.
  5. G. S. Konstantinou and V. G. Agelidis, "Performance evaluation of half-bridge cascaded multilevel converters operated with multicarrier sinusoidal PWM techniques," in Proc. IEEE Industrial Electronics and Applications Conf., pp. 3399-3404, 2009.
  6. D. Zhong, L. M. Tolbert, J. N. Chiasson, and B. Ozpineci, "Reduced switching-frequency active harmonic elimination for multilevel converters," IEEE Trans. Ind. Electron., Vol. 55, No. 4, pp. 1761-1770, Apr. 2008. https://doi.org/10.1109/TIE.2008.917068
  7. D. Zhong, L. M. Tolbert, and J. N. Chiasson, "Active harmonic elimination for multilevel converters," IEEE Trans. Power Electron., Vol. 21, No. 2, pp. 459-469, Mar. 2006. https://doi.org/10.1109/TPEL.2005.869757
  8. B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, "Harmonic optimization of multilevel converters using genetic algorithms," IEEE Power Electron. Lett., Vol. 3, No. 3, pp. 92-95, Sep. 2005. https://doi.org/10.1109/LPEL.2005.856713
  9. S. Sirisukprasert, L. J. Sheng, and L. T. Hua, "Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters," IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 875-881, Aug. 2002. https://doi.org/10.1109/TIE.2002.801226
  10. M. Glinka and R. Marquardt, "A new AC/AC multilevel converter family," IEEE Trans. Ind. Electron., Vol. 52, No. 3, pp. 662-669, Jun. 2005. https://doi.org/10.1109/TIE.2005.843973
  11. L. Pu, W. Yue, and C. Wulong, "Grouping-sorting optimized model predictive control of modular multilevel converter with reduced computational load," in 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Jul. 2015.
  12. B. Xia, Y. Li, and Z. Li, "A distributed voltage balancing method for modular multilevel converter," in IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017-ECCE Asia), Jul. 2017.
  13. Q. Tu and Z. Xu, "Impact of sampling frequency on harmonic distortion for modular multilevel converter," IEEE Trans. on Power Delivery, Vol. 26, No. 1, pp. 298-306, Dec. 2010. https://doi.org/10.1109/TPWRD.2010.2078837
  14. H. R. Campos and F. M. David, "Selective harmonic elimination for the modular multilevel converter," North American Power Symposium (NAPS), Sep. 2016.