Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
권호 표지

Novel Wafer Warpage Measurement Method for 3D Stacked IC

3D 적층 IC제조를 위한 웨이퍼 휨 측정법

  • Kim, Sungdong (Dept. of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Jung, Juhwan (DB Hitek)
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 정주환 (동부하이텍)
  • Received : 2018.12.14
  • Accepted : 2018.12.20
  • Published : 2018.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.

Keywords

References

  1. Al-Sarawi, S. F., Abbott, D., and Franzon, P. D. "A review of 3-D packaging technology," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 21(1), pp. 2-14, (1998). https://doi.org/10.1109/96.659500
  2. Lau, J. H., Li, M., Tian, D., Fan, N., Kuah, E., Kai, W., Li, M., Hao, J., Cheung, Y., Li, Z., Tan, K., Beica, R. Taylor, T., Ko, C., Yang, H., Chen, Y., Lm, S., Lee, N., Ran, J., Xi, C., Wee, K., and Yong, Q., "Warpage and thermal characterization of fan-out wafer-level packaging," IEEE Transactions on Components, Packaging and Manufacturing Technology, 7(10), 1729-1738, (2017). https://doi.org/10.1109/TCPMT.2017.2715185
  3. E. S. Lee, W. B. Kim, I. S. Song, C. Y. Moon, H. C. Kim, and K. J. Chun, "A novel wafer-level-packaging scheme using solder," Journal of the Semiconductor & Display Equipment Technology, 3(3), pp. 5-9, (2004).
  4. Pizzagalli, A., Thibault B., and Rozalia B., "3D technology applications market trends & key challenges," Advanced Semiconductor Manufacturing Conference (ASMC), 25th Annual SEMI. IEEE, pp. 78-81, (2014).
  5. Y. H. Cho, S. E. Kim and S. Kim, "Wafer Level Bonding Technology for 3D Stacked IC," Journal of the Microelectronics & Packaging Society, 20(1), pp. 7-13 (2013). https://doi.org/10.6117/kmeps.2013.20.1.007
  6. S. Shin, M. Park, S. E. Kim, and S. Kim, "Effects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process," Journal of the Microelectronics & Packaging Society, 20(3), pp. 71-74, (2013). https://doi.org/10.6117/kmeps.2013.20.3.071
  7. Ding, H., Powell, R. E., Hanna, C. R., & Ume, I. C. "Warpage measurement comparison using shadow moire and projection moire methods," IEEE Transactions on Components and Packaging Technologies, 25(4), pp. 714-721. (2002). https://doi.org/10.1109/TCAPT.2002.808010
  8. S. Son, H. Kihm and H. S. Yang, "Effect of Die Bonding Epoxy on the Warpage and Optical Performance of Mobile Phone Camera Packages," Journal of the Semiconductor & Display Equipment Technology, 15(4), pp. 1-9, (2016).
  9. SEMI Draft Document 5409, "New Standard: Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks."
  10. Verma, K., and Han, B. "Warpage measurement on dielectric rough surfaces of microelectronics devices by far infrared Fizeau interferometry," Journal of Electronic Packaging, 122(3), pp. 227-232, (2000). https://doi.org/10.1115/1.1286315
  11. Dieter K. Schroder, Semiconductor Material and Device Characterization, John Wiley & Sons, pp.37-38, (2006).