Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
권호 표지

A Study of Warpage Analysis According to Influence Factors in FOWLP Structure

FOWLP 구조의 영향 인자에 따른 휨 현상 해석 연구

  • Jung, Cheong-Ha (Electronic Packaging Research Center, Kangnam University) ;
  • Seo, Won (Electronic Packaging Research Center, Kangnam University) ;
  • Kim, Gu-Sung (Electronic Packaging Research Center, Kangnam University)
  • 정청하 (강남대학교 전자패키지연구소) ;
  • 서원 (강남대학교 전자패키지연구소) ;
  • 김구성 (강남대학교 전자패키지연구소)
  • Received : 2018.11.21
  • Accepted : 2018.12.18
  • Published : 2018.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

Keywords

References

  1. Cha Gyu Song, Sung-Hoon Choa, "Numerical Study of Warpage and Stress for the Ultra Thin Package," J. Microelectron. Packag. Soc., 17(4), pp. 49-60, (2010).
  2. H. Tang, J. Nguyen, J. Zhang and I. Chien, "Warpage Study of a Package on Package Configuration," 2007 International Symposium on High Density packaging and Microsystem Integration, Shanghai, pp. 1-5, (2007).
  3. W. Sun, W. H. Zhu, C. K. Wang, A. Y. S. Sun and H. B. Tan, "Warpage simulation and DOE analysis with application in package-on-package development," EuroSimE 2008 - International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, Freiburg im Breisgau, pp. 1-8, (2008).
  4. Kyoung-Ho Kim, Hyouk Lee, Jin-Wook Jeong, Ju-Hyung Kim, Sung-Hoon Choa1, "Numerical Analysis of Warpage and Stress for 4-layer Stacked FBGA Package," J. Microelectron. Packag. Soc., 19(2), pp. 10-13, (2012).
  5. Man Sung Choi, Kwang Sun Kim, "Experimental Analysis and Optimization of $CF_4/O_2$ Plasma Etching Process," Journal of the Semiconductor & Display Technology, 8(4), pp. 1-5, (2009).
  6. M.K.LEE, S.H.Choa, J.W.Jeong, J,Y.Ock, "Study of fan-out wafer level package to optimize the warpage," Korean Society for Precision Engineering, pp. 10-19, (2014).
  7. Wei Keat Loh, R. Kulterman, H. Fu and M. Tsuriya, "Recent trends of package warpage and measurement metrologies," 2016 International Conference on Electronics Packaging (ICEP), Sapporo, pp. 89-93, (2016).
  8. Y. Bin, W. Xiaofeng and Z. Yabing, "The Study of Thermally Induced Warpage of BGA Package during Reflow Soldering," 2018 19th International Conference on Electronic Packaging Technology (ICEPT), Shanghai, pp. 1411-1414, (2018).
  9. A. B. Denoyo, "Warpage resolution for Ball Grid Array (BGA) package in a fully integrated assembly," 2012 13th International Conference on Electronic Packaging Technology & High Density Packaging, Guilin, pp. 419-422, (2012).
  10. J. Jang, K. Suk, J. Park, K. Paik and S. Lee, "Warpage Behavior and Life Prediction of a Chip-on-Flex Package Under a Thermal Cycling Condition," in IEEE Transactions on Components, Packaging and Manufacturing Technology, 4(7), pp. 1144-1151, (2014). https://doi.org/10.1109/TCPMT.2014.2325975