Fig. 1 The layers of PCI Express architecture.
Fig. 2 Transaction layer packet (TLP).
Fig. 3 Topology of PCI Express system[12].
Fig. 4 Basic options for Xilinx XDMA IP.
Fig. 5 Xilinx ZC706 EVM board [11].
Fig. 6 Block diagram of XDMA evaluation system
Fig. 7 PCIe throughput vs. internal memory size.
Fig. 8 Write throughputs with different AXI options
Fig. 10 Write throughputs with different memory widths
Fig. 9 Read throughputs with different AXI options
Fig. 11 Read throughputs with different memory widths
Table. 1 FPGA PCIe framework comparison.
Table. 2 PCIe solution portfolio in Xilinx FPGA.
Table. 3 Performance with different memory widths
References
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