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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Analysis of a Parasitic-Diode-Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

  • Song, Bo Bae (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Lee, Byung Seok (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Yang, Yil Suk (ICT Materials & Components Research Laboratory, ETRI) ;
  • Koo, Yong-Seo (Department of Electronics and Electrical Engineering, Dankook University)
  • Received : 2016.01.10
  • Accepted : 2017.02.23
  • Published : 2017.10.01
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Abstract

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

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References

  1. M.D. Ker and C.C. Yen, "Investigation and Design of Onchip Power-Rail ESD Clamp Circuits without Suffering Latch Up-like Failure During System-Level ESD Test," IEEE J. Solid-State Circuits, vol. 43, no. 11, Nov. 2008, pp. 2533-2545. https://doi.org/10.1109/JSSC.2008.2005451
  2. J.Y. Lee, "Analysis of SCR, MVSCR, LVTSCR with I-V Characteristic and Turn-on-Time," J. Inst. Korean. Electr. Electron. Eng., vol. 20, no. 3, 2016, pp. 295-398.
  3. V.A. Vashchenko, et al., "High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps," IEEE Trans. Device Mater. Rel., vol. 4, no. 2, 2004, pp. 273-280. https://doi.org/10.1109/TDMR.2004.826584
  4. M.P.J. Mergens et al., "High Holding Current SCRs (HHISCR) for ESD Protection and Latch-up Immune IC Operation," Electr. Overstress/Electronstatic Discharge Symp., Charlotte,NC, USA, Oct. 6-10, 2002, pp. 10-17.
  5. O. Quittard et al., "ESD Protection for High-voltage CMOS Technologies," Electr. Overstress/Electronstatic Discharge Symp., Tucson, AZ, USA, Sept. 10-15, 2006, pp. 77-86.
  6. B. Keppens et al., "ESD Protection Solutions for High Voltage Technologies," Electri. Overstress/Electronstatic Discharge Symp., Grapevine, TX, USA, Sept. 19-23, 2004, pp. 1-10.
  7. Y.S. Koo, et al., "Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology," Microelectron. J., vol. 40, no. 6, June 2009, pp. 1007-1012. https://doi.org/10.1016/j.mejo.2009.01.001
  8. J.W. Jung and Y.S. Koo, "Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20V Power Clamp," ETRI J., vol. 37, no. 1, Feb. 2015, pp. 97-106. https://doi.org/10.4218/etrij.15.0114.0730
  9. J.E. Barth et al., "TLP Calibration, Correlation, Standards, and New Techniques," Electr. Overstress/Electronstatic Discharge Symp., Anaheim, CA, USA, Sept. 26-28, 2000, pp. 85-96.
  10. S.L. Jang, L.S. Lin, and S.H. Li, "Temperature-Dependent Dynamic Triggering Characteristics of SCR-Type ESD Protection Circuit," Solid-State Electron., vol. 45, no. 12, Dec. 2001, pp. 2005-2009. https://doi.org/10.1016/S0038-1101(01)00243-X
  11. J.E. Barth et al., "TLP Calibration, Correlation, Standards, and New Techniques," Electr. Overstress/Electronstatic Discharge Symp. Proc., Anaheim, CA, USA, Sept. 26-28, 2000, pp 85-96.