한국전자파학회논문지 (The Journal of Korean Institute of Electromagnetic Engineering and Science)

  • 제28권10호
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  • Pages.832-835
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  • 2017
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  • 1226-3133(pISSN)
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  • 2288-226X(eISSN)
한국전자파학회 (The Korean Institute of Electromagnetic Engineering and Science)
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65-nm CMOS 공정을 이용한 V-Band 차동 저잡음 증폭기 설계

Design of V-Band Differential Low Noise Amplifier Using 65-nm CMOS

  • 김동욱 (성균관대학교 정보통신대학) ;
  • 서현우 (성균관대학교 정보통신대학) ;
  • 김준성 (성균관대학교 정보통신대학) ;
  • 김병성 (성균관대학교 정보통신대학)
  • Kim, Dong-Wook (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Seo, Hyun-Woo (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jun-Seong (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Byung-Sung (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2017.08.17
  • 심사 : 2017.10.18
  • 발행 : 2017.10.31
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초록

본 논문은 고속 무선 데이터 통신을 위한 V-band 차동 저잡음 증폭기를 65-nm CMOS 공정을 이용하여 설계한 결과를 제시한다. 설계한 저잡음 증폭기는 3단 공통소스 구조이며, MOS 커패시터를 이용한 커패시턴스 중화 기법을 적용하였고, 트랜스포머를 이용하여 각 단의 임피던스 정합을 구현하였다. 제작한 저잡음 증폭기는 63 GHz에서 최대 이득 23 dB을 보이며, 3 dB 대역폭은 6 GHz이다. 제작한 칩의 크기는 패드를 포함하여 $0.3mm^2$이며, 1.2 V 공급 전원에서 32 mW의 전력을 소비한다.

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

키워드

참고문헌

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