KSII Transactions on Internet and Information Systems (TIIS)

  • 제11권5호
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  • Pages.2680-2700
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  • 2017
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  • 1976-7277(pISSN)
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  • 1976-7277(eISSN)
한국인터넷정보학회 (Korean Society for Internet Information)
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Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m)

  • Mathe, Sudha Ellison (Department of Electronics and Communication Engineering, National Institute of Technology-Warangal) ;
  • Boppana, Lakshmi (Department of Electronics and Communication Engineering, National Institute of Technology-Warangal)
  • 투고 : 2016.08.29
  • 심사 : 2017.02.22
  • 발행 : 2017.05.31
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초록

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

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