JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors

  • Park, Jungjin (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Hyungjin (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Kwon, Min-Woo (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Hwang, Sungmin (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Baek, Myung-Hyun (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Lee, Jeong-Jun (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Jang, Taejin (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University) ;
  • Park, Byung-Gook (Inter-university Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University)
  • Received : 2016.08.24
  • Accepted : 2016.11.01
  • Published : 2017.04.30
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Abstract

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

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References

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